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/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
52 mode "640x480-75"
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
H A Ds3fb.rst39 lower pixclocks (maximum usually between 50-60 MHz, depending on specific
40 hardware, i get best results from plain S3 Trio32 card - about 75 MHz). This
/openbmc/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
49 "mac7", 75, 640, 870, 17457, 80, 32, 42, 3, 80, 3,
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
65 "mac12", 75, 800, 600, 20203, 144, 32, 21, 1, 80, 3,
[all …]
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
90 /* Register values for 1024x768, 75Hz mode (17) */
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
135 /* Register values for 832x624, 75Hz mode (13) */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
[all …]
H A Dcontrolfb.h97 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
126 {{-1,-1}}, /* 640x870, 75Hz (portrait) */
131 {{ 2, 2}}, /* 800x600, 75Hz */
132 {{ 1, 2}}, /* 832x624, 75Hz */
135 {{ 1, 2}}, /* 1024x768, 75Hz (VESA) */
136 {{ 1, 2}}, /* 1024x768, 75Hz */
137 {{ 1, 2}}, /* 1152x870, 75Hz */
138 {{ 0, 1}}, /* 1280x960, 75Hz */
139 {{ 0, 1}}, /* 1280x1024, 75Hz */
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
74 /* 1280x1024, 75Hz (20) */
86 /* 1280x960, 75Hz (19) */
98 /* 1152x870, 75Hz (18) */
110 /* 1024x768, 75Hz (17) */
122 /* 1024x768, 75Hz (16) */
158 /* 832x624, 75Hz (13) */
172 /* 800x600, 75Hz (12) */
232 /* 640x870, 75Hz Portrait (7) */
[all …]
/openbmc/openbmc/meta-nuvoton/recipes-nuvoton/program-edid/program-edid/
H A Dedid.json63 "Pixel clock (MHz)": 154.0,
98 "Pixel clock (MHz)": 25.17,
116 "Pixel clock (MHz)": 170,
132 "1024x768 @ 75 Hz": true,
134 "1152x870 @ 75 Hz (Apple Macintosh II)": true,
135 "1280x1024 @ 75 Hz": true,
139 "640x480 @ 75 Hz": true,
145 "800x600 @ 75 Hz": true,
146 "832x624 @ 75 Hz": true,
165 "Frequency": 75,
/openbmc/linux/arch/arm/mach-omap2/
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
87 * (OR sysclk * 75 / 244) in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
103 num = 75; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
/openbmc/linux/tools/edid/
H A Dedid.S152 Bit 2 640x480 @ 75 Hz
158 Bit 6 800x600 @ 75 Hz
159 Bit 5 832x624 @ 75 Hz
163 Bit 1 1024x768 @ 75 Hz
164 Bit 0 1280x1024 @ 75 Hz */
167 /* Bit 7 1152x870 @ 75 Hz (Apple Macintosh II)
181 /* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */
262 to 10 MHz multiple (10-2550 MHz) */
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_arcturus.h515 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
516 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz
517 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz
518 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz
519 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
520 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz
525 uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz
529 uint16_t GfxclkFidle; // In MHz
532 uint16_t GfxclkDsMaxFreq; // In MHz
632 uint16_t BasePerformanceFrequencyCap; //In Mhz
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg49 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
114 # bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination)
116 # bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination)
129 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
197 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
/openbmc/u-boot/board/mpr2/
H A Dlowlevel_init.S76 * Spansion S29GL256N11 @ 48 MHz
84 * Samsung K4S511632B-UL75 @ 48 MHz
85 * Micron MT48LC32M16A2-75 @ 48 MHz
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dclock.h50 PLL_USB, /* USB PLL, fixed at 480MHZ */
88 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
124 SAI2_CLK_ROOT = 75,
230 CCGR_LCDIF = 75,
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
47 # bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
119 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
177 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
178 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemux86-64/
H A Dxorg.conf8 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
14 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemuarm/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemuppc/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemush4/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemux86/
H A Dxorg.conf8 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
14 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
/openbmc/linux/drivers/net/wan/
H A Dslic_ds26522.c99 /* RSYSCLK=2.048MHz, RSYNC-Output */ in ds26522_e1_spec_config()
106 /* TSYSCLK=2.048MHz, TSYNC-Output */ in ds26522_e1_spec_config()
127 /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */ in ds26522_e1_spec_config()
131 /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */ in ds26522_e1_spec_config()
/openbmc/u-boot/board/sysam/stmark2/
H A Dsbf_dram_init.S37 * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
38 * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
41 * / \ DDR2 can't be clocked lower than 125Mhz
47 /* cpu / 2 = 125 Mhz for 480 Mhz pll */
57 * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
/openbmc/linux/drivers/clk/
H A Dclk-vt8500.c380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
/openbmc/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dinitvals_phy.h29 RF_REG_PAIR(0, 13, 0x00), /* 40mhz xtal */
30 /* RF_REG_PAIR(0, 13, 0x13), */ /* 20mhz xtal */
201 { 75, 0x60 },
223 { 75, 0x5e },
233 { 75, 0x5c },
242 { 75, 0x60 },
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg114 # bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
173 # bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
175 # bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
187 # bit 8: 1, add sample stage required for > 266Mhz
247 # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
248 # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
H A Dkwbimage_128M16_1.cfg114 # bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM
173 # bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0]
175 # bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1]
187 # bit 8: 1, add sample stage required for f > 266 MHz
247 # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
248 # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm

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