Home
last modified time | relevance | path

Searched +full:65 +full:mhz (Results 1 – 25 of 197) sorted by relevance

12345678

/openbmc/u-boot/board/ge/bx50v3/
H A Dbx50v3.c304 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ in mx6_rgmii_rework()
311 /* set to 125 MHz from local PLL source */ in mx6_rgmii_rework()
418 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2) in enable_videopll()
426 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz in enable_videopll()
459 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ in setup_display_b850v3()
507 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */ in setup_display_bx50v3()
778 env_set("videoargs", "video=LVDS-1:1024x768@65"); in board_late_init()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/omap3-pandora/
H A Dfb.modes1 mode "800x480-65"
2 # D: 36.001 MHz, H: 34.124 kHz, V: 64.998 Hz
/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp157c-ed1-u-boot.dtsi140 /* VCO = 1300.0 MHz => P = 650 (CPU) */
147 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
149 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
154 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
161 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dclock.h50 PLL_USB, /* USB PLL, fixed at 480MHZ */
88 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
114 DRAM_ALT_CLK_ROOT = 65,
224 CCGR_SEMA2 = 65,
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-xilinx.yaml38 - description: Master/Core clock, has to be >= 125 MHz
39 for SS operation and >= 60MHz for HS operation.
130 interrupts = <0 65 4>, <0 69 4>;
/openbmc/linux/arch/x86/kernel/cpu/
H A Dtransmeta.c27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
/openbmc/linux/drivers/net/wireless/ath/wcn36xx/
H A Dtxrx.c71 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
91 { 65, 0, RX_ENC_HT, RX_ENC_FLAG_HT_GF, RATE_INFO_BW_20 },
134 /* 11ac 20 MHz 800ns GI MCS 0-8 */
135 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
156 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
166 /* 11ac 40 MHz 800ns GI MCS 0-9 */
187 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
195 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
202 /* 11ac 80 MHz 800ns GI MCS 0-7 */
215 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dadm1021.rst119 are possible between -65 and +127 degrees, with a resolution of one degree.
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
150 didn't have these sensors. Next generations of Xeon processors (533 MHz
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dhu-Szentes-Battonya23 # T 538000000 8MHz 3/4 NONE QAM64 8k 1/4 NONE
25 # C.multiplex UHF-65:
H A Dlt-All238 [kanalas 65]
288 #T 786000000 8MHz AUTO NONE QAM64 8k 1/16 NONE # kanalas 60
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
41 clock-frequency = <396000000>; // 396 MHz ppc core
72 bus-frequency = <66000000>; // 66 MHz ips bus
289 interrupts = <65 0x8>;
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h99 MXL_XCPU_PID_FLT_CFG_CMD = 65,
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
433 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
/openbmc/linux/drivers/clk/versatile/
H A Dclk-icst.c108 * 33 or 25 MHz respectively. in vco_get()
263 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
268 /* Slam to closest 0.25 MHz */ in icst_round_rate()
274 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
275 * select 25 MHz in icst_round_rate()
416 .rd_max = 65,
439 /* Minimum 12 MHz, VDW = 4 */
442 * Maximum 160 MHz, VDW = 152 for all core modules, but
444 * go to 200 MHz (max VDW = 192).
457 /* Minimum 3 MHz, VDW = 4 */
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dfc0012.c217 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
348 -63, -65, -54, -60, in fc0012_get_rf_strength()
351 65, 63, 61, 58, in fc0012_get_rf_strength()
411 .frequency_min_hz = 37 * MHz, /* estimate */
412 .frequency_max_hz = 862 * MHz, /* estimate */
H A Dfc0013.c370 /* fix for frequency less than 45 MHz */ in fc0013_set_params()
507 -63, -65, -54, -60, in fc0013_get_rf_strength()
510 65, 63, 61, 58, in fc0013_get_rf_strength()
569 .frequency_min_hz = 37 * MHz, /* estimate */
570 .frequency_max_hz = 1680 * MHz, /* CHECK */
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c311 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ in setup_display()
344 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ in setup_display()
365 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ in ar8035_phy_fixup()
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
69 .m2 = {.min = 65, .max = 130},
93 .m2 = {.min = 65, .max = 130},
628 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
631 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
638 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
639 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
640 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-vt8500.c380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
438 else if (freq >= 65) in wm8750_get_filter()
/openbmc/linux/scripts/
H A Dextract_xc3028.pl590 # Firmware 48, type: SCODE FW HAS IF (0x60000000), IF = 3.28 MHz id: (0000000000000000), size: 192
600 # Firmware 49, type: SCODE FW HAS IF (0x60000000), IF = 3.30 MHz id: (0000000000000000), size: 192
610 # Firmware 50, type: SCODE FW HAS IF (0x60000000), IF = 3.44 MHz id: (0000000000000000), size: 192
620 # Firmware 51, type: SCODE FW HAS IF (0x60000000), IF = 3.46 MHz id: (0000000000000000), size: 192
630 …# Firmware 52, type: SCODE FW DTV6 ATSC OREN36 HAS IF (0x60210020), IF = 3.80 MHz id: (0000000000…
640 # Firmware 53, type: SCODE FW HAS IF (0x60000000), IF = 4.00 MHz id: (0000000000000000), size: 192
650 …# Firmware 54, type: SCODE FW DTV6 ATSC TOYOTA388 HAS IF (0x60410020), IF = 4.08 MHz id: (0000000…
660 # Firmware 55, type: SCODE FW HAS IF (0x60000000), IF = 4.20 MHz id: (0000000000000000), size: 192
670 …# Firmware 56, type: SCODE FW MONO HAS IF (0x60008000), IF = 4.32 MHz id: NTSC/M Kr (000000000000…
680 # Firmware 57, type: SCODE FW HAS IF (0x60000000), IF = 4.45 MHz id: (0000000000000000), size: 192
[all …]
/openbmc/u-boot/board/CarMediaLab/flea3/
H A Dflea3.c139 gpio_direction_output(65, 1); in board_early_init_f()
147 /* Set the core to run at 532 Mhz */ in board_early_init_f()
/openbmc/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c17 #define REF_FREQ_2595 1432 /* 14.33 MHz (exact 14.31818) */
20 #define MAX_FREQ_2595 15938 /* 159.38 MHz (really 170.486) */
21 #define MIN_FREQ_2595 8000 /* 80.00 MHz ( 85.565) */
23 #define ABS_MIN_FREQ_2595 1000 /* 10.00 MHz (really 10.697) */
136 8000, (3 << 6) | 20, 9}, /* 7395 ps / 135.2273 MHz */ in aty_var_to_pll_514()
138 10000, (1 << 6) | 19, 3}, /* 9977 ps / 100.2273 MHz */ in aty_var_to_pll_514()
140 13000, (1 << 6) | 2, 3}, /* 12509 ps / 79.9432 MHz */ in aty_var_to_pll_514()
142 14000, (2 << 6) | 8, 7}, /* 13394 ps / 74.6591 MHz */ in aty_var_to_pll_514()
144 16000, (1 << 6) | 44, 6}, /* 15378 ps / 65.0284 MHz */ in aty_var_to_pll_514()
146 25000, (1 << 6) | 15, 5}, /* 17460 ps / 57.2727 MHz */ in aty_var_to_pll_514()
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.h51 #define SPX5_PORTS 65
53 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */
200 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */
201 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */
202 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */

12345678