14549e789STom Rini// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 23d2d115aSPatrick Delaunay/* 33d2d115aSPatrick Delaunay * Copyright : STMicroelectronics 2018 43d2d115aSPatrick Delaunay */ 53d2d115aSPatrick Delaunay 63d2d115aSPatrick Delaunay#include <dt-bindings/clock/stm32mp1-clksrc.h> 73d2d115aSPatrick Delaunay#include "stm32mp157-u-boot.dtsi" 83d2d115aSPatrick Delaunay#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 93d2d115aSPatrick Delaunay 103d2d115aSPatrick Delaunay/ { 113d2d115aSPatrick Delaunay aliases { 123d2d115aSPatrick Delaunay mmc0 = &sdmmc1; 130ed232b1SPatrick Delaunay mmc1 = &sdmmc2; 143d2d115aSPatrick Delaunay i2c3 = &i2c4; 153d2d115aSPatrick Delaunay }; 168e166510SPatrick Delaunay 178e166510SPatrick Delaunay led { 188e166510SPatrick Delaunay compatible = "gpio-leds"; 198e166510SPatrick Delaunay 208e166510SPatrick Delaunay red { 218e166510SPatrick Delaunay label = "stm32mp:red:status"; 228e166510SPatrick Delaunay gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; 238e166510SPatrick Delaunay default-state = "off"; 248e166510SPatrick Delaunay }; 258e166510SPatrick Delaunay green { 268e166510SPatrick Delaunay label = "stm32mp:green:user"; 278e166510SPatrick Delaunay gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; 288e166510SPatrick Delaunay default-state = "on"; 298e166510SPatrick Delaunay }; 308e166510SPatrick Delaunay orange { 318e166510SPatrick Delaunay label = "stm32mp:orange:status"; 328e166510SPatrick Delaunay gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; 338e166510SPatrick Delaunay default-state = "off"; 348e166510SPatrick Delaunay }; 358e166510SPatrick Delaunay blue { 368e166510SPatrick Delaunay label = "stm32mp:blue:user"; 378e166510SPatrick Delaunay gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; 388e166510SPatrick Delaunay }; 398e166510SPatrick Delaunay }; 403d2d115aSPatrick Delaunay}; 413d2d115aSPatrick Delaunay 42*e74b74c5SPatrick Delaunay&clk_hse { 43*e74b74c5SPatrick Delaunay st,digbypass; 44*e74b74c5SPatrick Delaunay}; 45*e74b74c5SPatrick Delaunay 463d2d115aSPatrick Delaunay&uart4_pins_a { 473d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 483d2d115aSPatrick Delaunay pins1 { 493d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 503d2d115aSPatrick Delaunay }; 513d2d115aSPatrick Delaunay pins2 { 523d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 533d2d115aSPatrick Delaunay }; 543d2d115aSPatrick Delaunay}; 553d2d115aSPatrick Delaunay 563d2d115aSPatrick Delaunay&i2c4_pins_a { 573d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 583d2d115aSPatrick Delaunay pins { 593d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 603d2d115aSPatrick Delaunay }; 613d2d115aSPatrick Delaunay}; 623d2d115aSPatrick Delaunay 633d2d115aSPatrick Delaunay&uart4 { 643d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 653d2d115aSPatrick Delaunay}; 663d2d115aSPatrick Delaunay 673d2d115aSPatrick Delaunay&i2c4 { 683d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 693d2d115aSPatrick Delaunay}; 703d2d115aSPatrick Delaunay 713d2d115aSPatrick Delaunay&pmic { 723d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 733d2d115aSPatrick Delaunay}; 743d2d115aSPatrick Delaunay 75a674313cSPatrick Delaunay&rcc { 763d2d115aSPatrick Delaunay st,clksrc = < 773d2d115aSPatrick Delaunay CLK_MPU_PLL1P 783d2d115aSPatrick Delaunay CLK_AXI_PLL2P 793d2d115aSPatrick Delaunay CLK_MCU_PLL3P 803d2d115aSPatrick Delaunay CLK_PLL12_HSE 813d2d115aSPatrick Delaunay CLK_PLL3_HSE 823d2d115aSPatrick Delaunay CLK_PLL4_HSE 833d2d115aSPatrick Delaunay CLK_RTC_LSE 843d2d115aSPatrick Delaunay CLK_MCO1_DISABLED 853d2d115aSPatrick Delaunay CLK_MCO2_DISABLED 863d2d115aSPatrick Delaunay >; 873d2d115aSPatrick Delaunay 883d2d115aSPatrick Delaunay st,clkdiv = < 893d2d115aSPatrick Delaunay 1 /*MPU*/ 903d2d115aSPatrick Delaunay 0 /*AXI*/ 913d2d115aSPatrick Delaunay 0 /*MCU*/ 923d2d115aSPatrick Delaunay 1 /*APB1*/ 933d2d115aSPatrick Delaunay 1 /*APB2*/ 943d2d115aSPatrick Delaunay 1 /*APB3*/ 953d2d115aSPatrick Delaunay 1 /*APB4*/ 963d2d115aSPatrick Delaunay 2 /*APB5*/ 973d2d115aSPatrick Delaunay 23 /*RTC*/ 983d2d115aSPatrick Delaunay 0 /*MCO1*/ 993d2d115aSPatrick Delaunay 0 /*MCO2*/ 1003d2d115aSPatrick Delaunay >; 1013d2d115aSPatrick Delaunay 1023d2d115aSPatrick Delaunay st,pkcs = < 1038a07d5bfSPatrick Delaunay CLK_CKPER_HSE 1048a07d5bfSPatrick Delaunay CLK_FMC_ACLK 1058a07d5bfSPatrick Delaunay CLK_QSPI_ACLK 1068a07d5bfSPatrick Delaunay CLK_ETH_DISABLED 107*e74b74c5SPatrick Delaunay CLK_SDMMC12_PLL4P 1088a07d5bfSPatrick Delaunay CLK_DSI_DSIPLL 109b90f0e7cSPatrick Delaunay CLK_STGEN_HSE 1108a07d5bfSPatrick Delaunay CLK_USBPHY_HSE 1118a07d5bfSPatrick Delaunay CLK_SPI2S1_PLL3Q 1128a07d5bfSPatrick Delaunay CLK_SPI2S23_PLL3Q 1138a07d5bfSPatrick Delaunay CLK_SPI45_HSI 1148a07d5bfSPatrick Delaunay CLK_SPI6_HSI 1158a07d5bfSPatrick Delaunay CLK_I2C46_HSI 116*e74b74c5SPatrick Delaunay CLK_SDMMC3_PLL4P 1178a07d5bfSPatrick Delaunay CLK_USBO_USBPHY 1188a07d5bfSPatrick Delaunay CLK_ADC_CKPER 1198a07d5bfSPatrick Delaunay CLK_CEC_LSE 1208a07d5bfSPatrick Delaunay CLK_I2C12_HSI 1218a07d5bfSPatrick Delaunay CLK_I2C35_HSI 1228a07d5bfSPatrick Delaunay CLK_UART1_HSI 1238a07d5bfSPatrick Delaunay CLK_UART24_HSI 1248a07d5bfSPatrick Delaunay CLK_UART35_HSI 1258a07d5bfSPatrick Delaunay CLK_UART6_HSI 1268a07d5bfSPatrick Delaunay CLK_UART78_HSI 127*e74b74c5SPatrick Delaunay CLK_SPDIF_PLL4P 1288a07d5bfSPatrick Delaunay CLK_FDCAN_PLL4Q 1298a07d5bfSPatrick Delaunay CLK_SAI1_PLL3Q 1308a07d5bfSPatrick Delaunay CLK_SAI2_PLL3Q 1318a07d5bfSPatrick Delaunay CLK_SAI3_PLL3Q 1328a07d5bfSPatrick Delaunay CLK_SAI4_PLL3Q 133*e74b74c5SPatrick Delaunay CLK_RNG1_LSI 134*e74b74c5SPatrick Delaunay CLK_RNG2_LSI 1358a07d5bfSPatrick Delaunay CLK_LPTIM1_PCLK1 1368a07d5bfSPatrick Delaunay CLK_LPTIM23_PCLK3 137*e74b74c5SPatrick Delaunay CLK_LPTIM45_LSE 1383d2d115aSPatrick Delaunay >; 1393d2d115aSPatrick Delaunay 1403d2d115aSPatrick Delaunay /* VCO = 1300.0 MHz => P = 650 (CPU) */ 1413d2d115aSPatrick Delaunay pll1: st,pll@0 { 1423d2d115aSPatrick Delaunay cfg = < 2 80 0 0 0 PQR(1,0,0) >; 1433d2d115aSPatrick Delaunay frac = < 0x800 >; 1443d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1453d2d115aSPatrick Delaunay }; 1463d2d115aSPatrick Delaunay 1473d2d115aSPatrick Delaunay /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 1483d2d115aSPatrick Delaunay pll2: st,pll@1 { 1493d2d115aSPatrick Delaunay cfg = < 2 65 1 0 0 PQR(1,1,1) >; 1503d2d115aSPatrick Delaunay frac = < 0x1400 >; 1513d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1523d2d115aSPatrick Delaunay }; 1533d2d115aSPatrick Delaunay 154*e74b74c5SPatrick Delaunay /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 1553d2d115aSPatrick Delaunay pll3: st,pll@2 { 156*e74b74c5SPatrick Delaunay cfg = < 1 33 1 16 36 PQR(1,1,1) >; 157*e74b74c5SPatrick Delaunay frac = < 0x1a04 >; 1583d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1593d2d115aSPatrick Delaunay }; 1603d2d115aSPatrick Delaunay 161*e74b74c5SPatrick Delaunay /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 1623d2d115aSPatrick Delaunay pll4: st,pll@3 { 163*e74b74c5SPatrick Delaunay cfg = < 3 98 5 7 7 PQR(1,1,1) >; 1643d2d115aSPatrick Delaunay u-boot,dm-pre-reloc; 1653d2d115aSPatrick Delaunay }; 1663d2d115aSPatrick Delaunay}; 1673d2d115aSPatrick Delaunay 1683d2d115aSPatrick Delaunay/* SPL part **************************************/ 1693d2d115aSPatrick Delaunay/* MMC1 boot */ 1703d2d115aSPatrick Delaunay&sdmmc1_b4_pins_a { 1713d2d115aSPatrick Delaunay u-boot,dm-spl; 1723d2d115aSPatrick Delaunay pins { 1733d2d115aSPatrick Delaunay u-boot,dm-spl; 1743d2d115aSPatrick Delaunay }; 1753d2d115aSPatrick Delaunay}; 1763d2d115aSPatrick Delaunay 1773d2d115aSPatrick Delaunay&sdmmc1_dir_pins_a { 1783d2d115aSPatrick Delaunay u-boot,dm-spl; 1793d2d115aSPatrick Delaunay pins { 1803d2d115aSPatrick Delaunay u-boot,dm-spl; 1813d2d115aSPatrick Delaunay }; 1823d2d115aSPatrick Delaunay}; 1833d2d115aSPatrick Delaunay 1843d2d115aSPatrick Delaunay&sdmmc1 { 1853d2d115aSPatrick Delaunay u-boot,dm-spl; 1863d2d115aSPatrick Delaunay}; 1870ed232b1SPatrick Delaunay 1880ed232b1SPatrick Delaunay/* MMC2 boot */ 1890ed232b1SPatrick Delaunay&sdmmc2_b4_pins_a { 1900ed232b1SPatrick Delaunay u-boot,dm-spl; 1910ed232b1SPatrick Delaunay pins { 1920ed232b1SPatrick Delaunay u-boot,dm-spl; 1930ed232b1SPatrick Delaunay }; 1940ed232b1SPatrick Delaunay}; 1950ed232b1SPatrick Delaunay 1960ed232b1SPatrick Delaunay&sdmmc2_d47_pins_a { 1970ed232b1SPatrick Delaunay u-boot,dm-spl; 1980ed232b1SPatrick Delaunay pins { 1990ed232b1SPatrick Delaunay u-boot,dm-spl; 2000ed232b1SPatrick Delaunay }; 2010ed232b1SPatrick Delaunay}; 2020ed232b1SPatrick Delaunay 2030ed232b1SPatrick Delaunay&sdmmc2 { 2040ed232b1SPatrick Delaunay u-boot,dm-spl; 2050ed232b1SPatrick Delaunay}; 206