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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2.c644 (ar_mac[i][4] << 8) | ar_mac[i][5]; in hw_atl2_hw_multicast_list_set()
703 {0xfU, 0xffU}, /* 10Gbit */ in hw_atl2_hw_interrupt_moderation_set()
704 {0xfU, 0x1ffU}, /* 5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
705 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ in hw_atl2_hw_interrupt_moderation_set()
706 {0xfU, 0x1ffU}, /* 2.5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
707 {0xfU, 0x1ffU}, /* 1Gbit */ in hw_atl2_hw_interrupt_moderation_set()
711 {0x6U, 0x38U},/* 10Gbit */ in hw_atl2_hw_interrupt_moderation_set()
712 {0xCU, 0x70U},/* 5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
713 {0xCU, 0x70U},/* 5Gbit 5GS */ in hw_atl2_hw_interrupt_moderation_set()
714 {0x18U, 0xE0U},/* 2.5Gbit */ in hw_atl2_hw_interrupt_moderation_set()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac-bcma-mdio.c2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
85 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
130 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
141 for (i = 0; i < 5; i++) { in bcma_mdio_phy_init()
157 for (i = 0; i < 5; i++) { in bcma_mdio_phy_init()
178 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
/openbmc/linux/Documentation/networking/device_drivers/ethernet/marvell/
H A Docteontx2.rst151 5. RQ may be selected by RSS or by configuring MCAM rule with a RQ number.
161 5. NPC MCAM entries can be installed to divert pkt onto a different channel.
332 # tc class add dev <interface> parent 1: classid 1:1 htb rate 10Gbit prio 1
334 # tc class add dev <interface> parent 1: classid 1:2 htb rate 10Gbit prio 7
338 # tc class add dev <interface> parent 1: classid 1:1 htb rate 10Gbit prio 2 quantum 409600
340 # tc class add dev <interface> parent 1: classid 1:2 htb rate 10Gbit prio 2 quantum 188416
342 # tc class add dev <interface> parent 1: classid 1:3 htb rate 10Gbit prio 2 quantum 32768
/openbmc/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Diavf.rst104 - 5 MSI-X interrupt vectors and corresponding i40e CSRs
159 to 1Gbit for tc0 and 3Gbit for tc1.
164 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
165 max_rate 1Gbit 3Gbit
181 For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
H A Di40e.rst577 5 tx-usecs 5
580 maximum of 5 microseconds before indicating a receive or transmit was complete.
668 to 1Gbit for tc0 and 3Gbit for tc1.
673 queues 16@0 16@16 hw 1 mode channel shaper bw_rlimit min_rate 1Gbit 2Gbit
674 max_rate 1Gbit 3Gbit
690 For example: min_rate 1Gbit 3Gbit: Verify bandwidth limit using network
/openbmc/linux/Documentation/scsi/
H A Dbnx2fc.rst44 5. "Symbolic Name" in 'fcoeadm -i' output would display if bnx2fc has claimed
62 Speed: 10 Gbit
63 Supported Speed: 10 Gbit
/openbmc/u-boot/board/gdsys/common/
H A Dioep-fpga.c91 feature_ramconfig = (fpga_features & 0x0060) >> 5; in ioep_fpga_print_info()
129 if (versions & (1<<5)) in ioep_fpga_print_info()
233 feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); in ioep_fpga_print_info()
/openbmc/linux/tools/testing/selftests/net/
H A Dtcp_mmap.c28 * received 32768 MB (0 % mmap'ed) in 14.1157 s, 19.4732 Gbit
30 * received 32768 MB (0 % mmap'ed) in 14.6833 s, 18.7204 Gbit
32 * received 32768 MB (0 % mmap'ed) in 11.143 s, 24.6682 Gbit
34 * received 32768 MB (0 % mmap'ed) in 14.9056 s, 18.4413 Gbit
40 * received 32768 MB (99.9939 % mmap'ed) in 6.73792 s, 40.7956 Gbit
42 * received 32768 MB (99.9939 % mmap'ed) in 7.26732 s, 37.8238 Gbit
44 * received 32768 MB (99.9939 % mmap'ed) in 7.61661 s, 36.0893 Gbit
46 * received 32768 MB (99.9939 % mmap'ed) in 7.43764 s, 36.9577 Gbit
116 temp ^= *(unsigned long *)(zone + 5*sizeof(long)); in hash_zone()
303 printf("received %lg MB (%lg %% mmap'ed) in %lg s, %lg Gbit\n" in child_thread()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h19 /* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
29 #define VC3_MPAR_tRP 5
31 #define VC3_MPAR_tRCD 5
34 #define VC3_MPAR_CWL 5
38 #define VC3_MPAR_tWR 5
42 /* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
48 #define VC3_MPAR_CL 5
52 #define VC3_MPAR_tRP 5
54 #define VC3_MPAR_tRCD 5
57 #define VC3_MPAR_CWL 5
[all …]
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0.c304 /* the LRO timebase divider is 5 uS (0x61a), in hw_atl_b0_hw_offload_set()
548 (mac_addr[4] << 8) | mac_addr[5]; in hw_atl_b0_hw_mac_addr_set()
1089 (ar_mac[i][4] << 8) | ar_mac[i][5]; in hw_atl_b0_hw_multicast_list_set()
1143 {0xfU, 0xffU}, /* 10Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1144 {0xfU, 0x1ffU}, /* 5Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1145 {0xfU, 0x1ffU}, /* 5Gbit 5GS */ in hw_atl_b0_hw_interrupt_moderation_set()
1146 {0xfU, 0x1ffU}, /* 2.5Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1147 {0xfU, 0x1ffU}, /* 1Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1152 {0x6U, 0x38U},/* 10Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
1153 {0xCU, 0x70U},/* 5Gbit */ in hw_atl_b0_hw_interrupt_moderation_set()
[all …]
H A Dhw_atl_a0.c338 (mac_addr[4] << 8) | mac_addr[5]; in hw_atl_a0_hw_mac_addr_set()
796 (ar_mac[i][4] << 8) | ar_mac[i][5]; in hw_atl_a0_hw_multicast_list_set()
838 0x01CU, /* 10Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
839 0x039U, /* 5Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
840 0x039U, /* 5Gbit 5GS */ in hw_atl_a0_hw_interrupt_moderation_set()
841 0x073U, /* 2.5Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
842 0x120U, /* 1Gbit */ in hw_atl_a0_hw_interrupt_moderation_set()
/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dsch_ets.sh22 tc qdisc replace dev $swp2 root handle 3: tbf rate 1gbit \
38 devlink_tc_bind_pool_th_set $swp2 7 egress 4 5
40 devlink_tc_bind_pool_th_set $swp2 6 egress 4 5
41 devlink_tc_bind_pool_th_save $swp2 5 egress
42 devlink_tc_bind_pool_th_set $swp2 5 egress 4 5
52 devlink_tc_bind_pool_th_restore $swp2 5 egress
/openbmc/u-boot/doc/
H A DREADME.spear15 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC)
18 5. NAND controller (FSMC)
32 5. UART
H A DREADME.b4860qds41 outbound). Supports types 5, 6 (outbound only)
55 . Two 10-Gbit Ethernet controllers (10GEC)
56 . Six 1G/2.5-Gbit Ethernet controllers for network communications
112 5. 3 SGMII interfaces
174 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
204 0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
282 5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/
H A Daq_common.h50 #define HW_ATL_NIC_NAME "Marvell (aQuantia) AQtion 10Gbit Network Adapter"
61 #define AQ_NIC_RATE_10M BIT(5)
/openbmc/u-boot/board/freescale/ls1021aiot/
H A DREADME17 - One Gbit Etherent RGMII interface to 4-ports switch
23 - 12V@5A DC
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S49 * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4.
97 .word 0x92cc4d6e @ 5
264 cmp r3, #0x5 @ repeat 5 times
603 tRFC = 110ns/1Gbit, 160ns/2Gbit, 300ns/4Gbit
623 ldr r1, =0x00000531 @ Default set to 1Gbit
792 tRFC = 105ns/512Mbit, 127.5ns/1Gbit, 197.5ns/2Gbit, 327.5ns/4Gbit
812 ldr r1, =0x00000521 @ Default set to 1Gbit
826 mov r2, r1, lsr #5 @ Set CL
1345 add r3, r3, #0x05 @ dll1.1 = dll1.0 + (MADJ >> 2) + 5
1587 cmp r6, #5 @ passcnt >= 5
[all …]
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DREADME15 - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
42 - 5 V input supply from USB
/openbmc/u-boot/drivers/misc/
H A Dihs_fpga.c36 const uint REFLECTION_TEST_ROUNDS = 5;
40 const uint FPGA_DONE_WAIT_ROUND = 5;
265 FEATURE_CARRIERS_MASK = GENMASK(5, 4), in get_features()
406 VERSIONS_SFP = BIT(5), in get_versions()
489 FEATURE_RAM_MASK = 0x7 << 5, in get_features()
490 FEATURE_RAM_DDR2_32BIT = 0x0 << 5, in get_features()
491 FEATURE_RAM_DDR3_32BIT = 0x1 << 5, in get_features()
492 FEATURE_RAM_DDR3_48BIT = 0x2 << 5, in get_features()
693 printf(", 1Gbit/s"); in fpga_print_info()
696 printf(", 3Gbit/s"); in fpga_print_info()
[all …]
/openbmc/linux/drivers/edac/
H A Darmada_xp_edac.c250 case 0: /* 2GBit */ in axp_mc_read_config()
259 case 3: /* 1GBit */ in axp_mc_read_config()
262 case 4: /* 4GBit */ in axp_mc_read_config()
265 case 5: /* 8GBit */ in axp_mc_read_config()
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman-dtsec.yaml16 (10GEC) for 10 Gbit/s speeds. Later versions of FMan use the Multirate
35 n = 1,..,5
60 n = 1,..5
/openbmc/linux/drivers/hwmon/pmbus/
H A Dpmbus_core.c735 mantissa = ((s16)((sensor->data & 0x7ff) << 5)) >> 5; in pmbus_reg2data_linear()
792 val = div_s64(val + 5LL, 10L); /* round closest */ in pmbus_reg2data_direct()
817 rv = 250 + (val - 1) * 5; in pmbus_reg2data_vid()
920 /* Convert to sign, 5 bit exponent, 10 bit mantissa */ in pmbus_data2reg_ieee754()
988 /* Convert to 5 bit exponent, 11 bit mantissa */ in pmbus_data2reg_linear()
1020 val = div_s64(val + 5LL, 10L); /* round closest */ in pmbus_data2reg_direct()
1456 u16 gbit; /* generic status bit */ member
1523 bool upper = !!(attr->gbit & 0xff00); /* need to check STATUS_WORD */ in pmbus_add_sensor_attrs_one()
1548 if (!ret && attr->gbit && in pmbus_add_sensor_attrs_one()
1554 attr->gbit); in pmbus_add_sensor_attrs_one()
[all …]
/openbmc/linux/drivers/media/pci/cobalt/
H A Dcobalt-driver.c170 case 5: return 4096; in get_payload_size()
179 case 1: return "2.5 Gbit/s"; in get_link_speed()
180 case 2: return "5 Gbit/s"; in get_link_speed()
181 case 3: return "10 Gbit/s"; in get_link_speed()
204 get_payload_size((ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5), in cobalt_pcie_status_show()
450 s->video_channel = 5; in cobalt_stream_struct_init()
457 s->video_channel = 5; in cobalt_stream_struct_init()
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg48 # bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
56 # bit7-4: 4, 5 cycle tRCD
57 # bit11-8: 4, 5 cyle tRP
58 # bit15-12: 5, 6 cyle tWR
76 # bit3-2: 3, Cs0size=1Gbit
103 # bit6-4: 5, CAS Latency (CL) 5
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
/openbmc/u-boot/board/dhelectronics/dh_imx6/
H A Ddh_imx6_spl.c203 * 2 Gbit DDR3 memory
221 * 4 Gbit DDR3 memory
247 .ralat = 5, /* Read additional latency */
266 .ralat = 5, /* Read additional latency */

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