Lines Matching +full:5 +full:gbit

19 /* Hynix H5TQ1G63BFA (1Gbit DDR3, x16) @ 3.20ns */
29 #define VC3_MPAR_tRP              5
31 #define VC3_MPAR_tRCD             5
34 #define VC3_MPAR_CWL              5
38 #define VC3_MPAR_tWR              5
42 /* Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16) @ 3.20ns */
48 #define VC3_MPAR_CL               5
52 #define VC3_MPAR_tRP              5
54 #define VC3_MPAR_tRCD             5
57 #define VC3_MPAR_CWL              5
61 #define VC3_MPAR_tWR              5
65 /* Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16) @ 3.20ns */
71 #define VC3_MPAR_CL               5
75 #define VC3_MPAR_tRP              5
77 #define VC3_MPAR_tRCD             5
80 #define VC3_MPAR_CWL              5
84 #define VC3_MPAR_tWR              5
88 /* Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16) - 2kb pages @ 3.20ns */
98 #define VC3_MPAR_tRP              5
100 #define VC3_MPAR_tRCD             5
103 #define VC3_MPAR_CWL              5
107 #define VC3_MPAR_tWR              5
111 /* Micron Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16) @ 3.20ns */
121 #define VC3_MPAR_tRP              5
123 #define VC3_MPAR_tRCD             5
126 #define VC3_MPAR_CWL              5
130 #define VC3_MPAR_tWR              5
228 #define MSCC_MEMPARM_MR2 ((VC3_MPAR_WL - 5) << 3)