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/openbmc/linux/arch/sh/mm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
9 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
12 On other systems (such as the SH-3 and 4) where an MMU exists,
28 The kernel page allocator limits the size of maximal physically
35 The page size is not necessarily 4KB. Keep this in mind when
77 bool "Support 32-bit physical addressing through PMB"
83 32-bits through the SH-4A PMB. If this is not set, legacy
84 29-bit physical addressing will be used.
91 bool "Support vsyscall page"
95 This will enable support for the kernel mapping a vDSO page
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/openbmc/linux/arch/loongarch/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
214 # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
247 default 4 if PGTABLE_4LEVEL
254 def_bool $(as-instr,x:pcalau12i \$t0$(comma)%pc_hi20(x))
257 def_bool $(as-instr,movfcsr2gr \$t0$(comma)\$fcsr0)
260 def_bool $(as-instr,vld \$vr0$(comma)\$a0$(comma)0)
263 def_bool $(as-instr,xvld \$xr0$(comma)\$a0$(comma)0)
266 def_bool $(as-instr,movscr2gr \$a0$(comma)\$scr0)
273 prompt "Page Table Layout"
277 Allows choosing the page table layout, which is a combination
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/openbmc/linux/arch/ia64/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 int "Page Table Levels" if !IA64_PAGE_SIZE_64KB
4 range 3 4 if !IA64_PAGE_SIZE_64KB
72 The Itanium Processor Family is Intel's 64-bit successor to
73 the 32-bit X86 line. The IA-64 Linux project has a home
74 page at <http://www.linuxia64.org/> and a mailing list at
75 <linux-ia64@vger.kernel.org>.
129 Select your IA-64 processor type. The default is Itanium.
130 This choice is safe for all IA-64 systems, but may not perform
141 prompt "Kernel page size"
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/openbmc/linux/arch/s390/mm/
H A Dpgalloc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Page table allocation functions
38 return register_sysctl("vm", page_table_sysctl) ? 0 : -ENOMEM; in page_table_register_sysctl()
66 if (current->active_mm == mm) { in __crst_table_upgrade()
67 S390_lowcore.user_asce = mm->context.asce; in __crst_table_upgrade()
76 unsigned long asce_limit = mm->context.asce_limit; in crst_table_upgrade()
78 /* upgrade should only happen from 3 to 4, 3 to 5, or 4 to 5 levels */ in crst_table_upgrade()
97 spin_lock_bh(&mm->page_table_lock); in crst_table_upgrade()
104 VM_BUG_ON(asce_limit != mm->context.asce_limit); in crst_table_upgrade()
107 __pgd = (unsigned long *) mm->pgd; in crst_table_upgrade()
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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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H A DREADME.mpc85xx-spin-table4 DDR is initialized and U-Boot relocates itself into DDR, the spin table is
5 accessible for core 0. It is part of release.S, within 4KB range after
9 Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
10 is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
11 the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
12 page translation for secondary cores to use this page of memory. Then 4KB
13 memory is copied from __secondary_start_page to the boot page, after flusing
14 cache because this page is mapped as normal DDR. Before copying the reset page,
19 When secondary cores boot up from 0xffff_f000 page, they only have one default
21 the new space. The new TLB covers the physical address of the spin table page,
/openbmc/linux/Documentation/arch/arm64/
H A Dmemory.rst8 Linux kernel. The architecture allows up to 4 levels of translation
9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
46 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
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/openbmc/linux/arch/parisc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
79 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 The PA-RISC microprocessor is designed by Hewlett-Packard and used
92 and later HP3000 series). The PA-RISC Linux project home page is
152 # unless you want to implement ACPI on PA-RISC ... ;-)
187 that can run on all 32-bit PA CPUs (albeit not optimally fast),
190 Specifying "PA8000" here will allow you to select a 64-bit kernel
196 Select this option for the PCX-L processor, as used in the
198 D200, D210, D300, D310 and E-class
203 Select this option for the PCX-T' processor, as used in the
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/openbmc/linux/arch/powerpc/include/asm/book3s/64/
H A Dradix-4k.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * For 4K page size supported index is 13/9/9/9
8 #define RADIX_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps 2^9 x 4K = 2MB
9 #define RADIX_PMD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps 2^9 x 2MB = 1GB
10 #define RADIX_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps 2^9 x 1GB = 512GB
11 #define RADIX_PGD_INDEX_SIZE 13 // size: 8B << 13 = 64KB, maps 2^13 x 512GB = 4PB
14 * One fragment per page
H A Dradix-64k.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * For 64K page size supported index is 13/9/9/5
9 #define RADIX_PMD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps 2^9 x 2MB = 1GB
10 #define RADIX_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps 2^9 x 1GB = 512GB
11 #define RADIX_PGD_INDEX_SIZE 13 // size: 8B << 13 = 64KB, maps 2^13 x 512GB = 4PB
14 * We use a 256 byte PTE page fragment in radix
H A Dhash-64k.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define H_PTE_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 64KB = 16MB
6 #define H_PMD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16MB = 16GB
7 #define H_PUD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16GB = 16TB
8 #define H_PGD_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 16TB = 4PB
11 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
12 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
13 * page_to_nid does a page->section->node lookup
37 * Define the address range of the kernel non-linear virtual area
46 #define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */
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H A Dhash-4k.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define H_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 4KB = 2MB
6 #define H_PMD_INDEX_SIZE 7 // size: 8B << 7 = 1KB, maps: 2^7 x 2MB = 256MB
7 #define H_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
8 #define H_PGD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 128GB = 64TB
11 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
18 * Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
31 * Define the address range of the kernel non-linear virtual area (61TB)
51 * Not supported by 4k linux page size
72 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
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/openbmc/linux/Documentation/mm/
H A Dpage_tables.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Page Tables
10 feature of all Unix-like systems as time went by. In 1985 the feature was
13 Page tables map virtual addresses as seen by the CPU into physical addresses
16 Linux defines page tables as a hierarchy which is currently five levels in
21 by the underlying physical page frame. The **page frame number** or **pfn**
22 is the physical address of the page (as seen on the external memory bus)
26 the last page of physical memory the external address bus of the CPU can
29 With a page granularity of 4KB and a address range of 32 bits, pfn 0 is at
31 and so on until we reach pfn 0xfffff at 0xfffff000. With 16KB pages pfs are
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H A Dvmemmap_dedup.rst2 .. SPDX-License-Identifier: GPL-2.0
13 The ``struct page`` structures are used to describe a physical page frame. By
14 default, there is a one-to-one mapping from a page frame to its corresponding
15 ``struct page``.
17 HugeTLB pages consist of multiple base page size pages and is supported by many
18 architectures. See Documentation/admin-guide/mm/hugetlbpage.rst for more
19 details. On the x86-64 architecture, HugeTLB pages of size 2MB and 1GB are
20 currently supported. Since the base page size on x86 is 4KB, a 2MB HugeTLB page
21 consists of 512 base pages and a 1GB HugeTLB page consists of 262144 base pages.
22 For each base page, there is a corresponding ``struct page``.
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/openbmc/linux/fs/proc/
H A Dtask_mmu.c1 // SPDX-License-Identifier: GPL-2.0
30 seq_put_decimal_ull_width(m, str, (val) << (PAGE_SHIFT-10), 8)
47 hiwater_vm = total_vm = mm->total_vm; in task_mem()
48 if (hiwater_vm < mm->hiwater_vm) in task_mem()
49 hiwater_vm = mm->hiwater_vm; in task_mem()
51 if (hiwater_rss < mm->hiwater_rss) in task_mem()
52 hiwater_rss = mm->hiwater_rss; in task_mem()
55 text = PAGE_ALIGN(mm->end_code) - (mm->start_code & PAGE_MASK); in task_mem()
56 text = min(text, mm->exec_vm << PAGE_SHIFT); in task_mem()
57 lib = (mm->exec_vm << PAGE_SHIFT) - text; in task_mem()
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/openbmc/linux/drivers/char/agp/
H A Dintel-gtt.c15 * /fairy-tale-mode off
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
52 /* This should undo anything done in ->setup() save the unmapping
57 * For chipsets that need to support old ums (non-gem) code, this
77 struct page *scratch_page;
92 #define INTEL_GTT_GEN intel_private.driver->gen
93 #define IS_G33 intel_private.driver->is_g33
94 #define IS_PINEVIEW intel_private.driver->is_pineview
95 #define IS_IRONLAKE intel_private.driver->is_ironlake
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/openbmc/linux/Documentation/filesystems/
H A Dproc.rst1 .. SPDX-License-Identifier: GPL-2.0
24 1.1 Process-Specific Subdirectories
36 3 Per-Process Parameters
37 3.1 /proc/<pid>/oom_adj & /proc/<pid>/oom_score_adj - Adjust the oom-killer
39 3.2 /proc/<pid>/oom_score - Display current oom-killer score
40 3.3 /proc/<pid>/io - Display the IO accounting fields
41 3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
42 3.5 /proc/<pid>/mountinfo - Information about mounts
44 3.7 /proc/<pid>/task/<tid>/children - Information about task children
45 3.8 /proc/<pid>/fdinfo/<fd> - Information about opened file
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/openbmc/linux/Documentation/admin-guide/cgroup-v1/
H A Dhugetlb.rst7 # mount -t cgroup -o hugetlb none /sys/fs/cgroup
25 …rsvd.max_usage_in_bytes # show max "hugepagesize" hugetlb reservations and no-reserve faults
26 …hugetlb.<hugepagesize>.rsvd.usage_in_bytes # show current reservations and no-reserve f…
46 hugetlb.64KB.limit_in_bytes
47 hugetlb.64KB.max_usage_in_bytes
48 hugetlb.64KB.numa_stat
49 hugetlb.64KB.usage_in_bytes
50 hugetlb.64KB.failcnt
51 hugetlb.64KB.rsvd.limit_in_bytes
52 hugetlb.64KB.rsvd.max_usage_in_bytes
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/openbmc/linux/Documentation/ABI/testing/
H A Dprocfs-smaps_rollup5 This file provides pre-summed memory information for a
15 and the procfs man page.
19 00100000-ff709000 ---p 00000000 00:00 0 [rollup]
20 Size: 1192 kB
21 KernelPageSize: 4 kB
22 MMUPageSize: 4 kB
23 Rss: 884 kB
24 Pss: 385 kB
25 Pss_Dirty: 68 kB
26 Pss_Anon: 301 kB
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/openbmc/linux/arch/mips/include/asm/
H A Dpgtable-64.h16 #include <asm/page.h>
21 #include <asm-generic/pgtable-nopmd.h>
23 #include <asm-generic/pgtable-nopud.h>
25 #include <asm-generic/pgtable-nop4d.h>
29 * Each address space has 2 4K pages as its page directory, giving 1024
31 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
32 * tables. Each page table is also a single 4K page, giving 512 (==
39 * fault address - VMALLOC_START.
43 /* PGDIR_SHIFT determines what a third-level page table entry can map */
45 #define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
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/openbmc/linux/include/xen/
H A Dpage.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/page.h>
7 /* The hypercall interface supports only 4KB page */
10 #define XEN_PAGE_MASK (~(XEN_PAGE_SIZE-1))
19 (pfn_to_page((unsigned long)(xen_pfn) >> (PAGE_SHIFT - XEN_PAGE_SHIFT)))
20 #define page_to_xen_pfn(page) \ argument
21 ((page_to_pfn(page)) << (PAGE_SHIFT - XEN_PAGE_SHIFT))
26 #define XEN_PFN_UP(x) (((x) + XEN_PAGE_SIZE-1) >> XEN_PAGE_SHIFT)
28 #include <asm/xen/page.h>
30 /* Return the GFN associated to the first 4KB of the page */
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/openbmc/u-boot/arch/arm/mach-uniphier/boot-device/
H A Dboot-device-pxs3.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "../sg-regs.h"
13 #include "boot-device.h"
16 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
17 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
18 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
19 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
20 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
21 {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
24 {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"},
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/openbmc/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #define PNV_OCXL_TL_BITS_PER_RATE 4
21 * 0b01 Invalidate just Page Walk Cache.
22 * 0b10 Invalidate TLB, Page Walk Cache, and any
26 /* Number and Page Size of translations to be invalidated */
37 /* Actual Page Size to be invalidated
38 * 000 4KB
39 * 101 64KB
44 /* Defines the large page select
45 * L=0b0 for 4KB pages
/openbmc/linux/drivers/net/ethernet/intel/iavf/
H A Diavf_alloc.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
15 iavf_mem_atq_ring = 4, /* ATQ descriptor ring */
16 iavf_mem_pd = 5, /* Page Descriptor */
17 iavf_mem_bp = 6, /* Backing Page - 4KB */
18 iavf_mem_bp_jumbo = 7, /* Backing Page - > 4KB */
/openbmc/u-boot/drivers/ddr/fsl/
H A Dddr3_dimm_params.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
8 * JEDEC standard No.21-C 4_01_02_11R18.pdf
27 * SPD byte4 - sdram density and banks
33 * 0100 4Gb 512MB
37 * SPD byte8 - module memory bus width
44 * SPD byte7 - module organiztion
46 * 000 4bits
61 if ((spd->density_banks & 0xf) < 7) in compute_ranksize()
62 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; in compute_ranksize()
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