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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,cmt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
26 - items:
27 - enum:
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-104-idi-48.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
87 #define IDI48_NGPIO 48
91 .mask = BIT((_id) / 8), \
96 IDI48_REGMAP_IRQ(0), IDI48_REGMAP_IRQ(1), IDI48_REGMAP_IRQ(2), /* 0-2 */
[all …]
/openbmc/linux/Documentation/arch/arm64/
H A Dmemory.rst12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
21 User addresses have bits 63:48 set to 0 while the kernel addresses have
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
24 mappings while the user pgd contains only user (non-global) mappings.
29 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
32 -----------------------------------------------------------------------
46 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
49 -----------------------------------------------------------------------
65 +--------+--------+--------+--------+--------+--------+--------+--------+
[all …]
/openbmc/linux/include/uapi/linux/
H A Ddccp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 * struct dccp_hdr - generic part of DCCP packet header
11 * @dccph_sport - Relevant port on the endpoint that sent this packet
12 * @dccph_dport - Relevant port on the other endpoint
13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
14 * @dccph_ccval - Used by the HC-Sender CCID
15 * @dccph_cscov - Parts of the packet that are covered by the Checksum field
16 * @dccph_checksum - Internet checksum, depends on dccph_cscov
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
18 * @dccph_type - packet type, see DCCP_PKT_ prefixed macros
[all …]
H A Dhdreg.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
[all …]
/openbmc/qemu/hw/ide/
H A Dide-internal.h5 * QEMU IDE Emulation -- internal header file
7 * non-internal declarations are in hw/include/ide-*.h
10 #include "hw/ide/ide-bus.h"
19 * ATA3-7: obsolete. */
45 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
59 /* ACS-2 T13/2015-D Table B.2 Command codes */
72 #define WIN_READ 0x20 /* 28-Bit */
73 #define WIN_READ_ONCE 0x21 /* 28-Bit w/o retries, obsolete since ATA5 */
75 #define WIN_READ_EXT 0x24 /* 48-Bit */
76 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <skylark@unaligned.org>
7 * 2007-2015 Joshua Kinard <kumba@gentoo.org>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
[all …]
/openbmc/linux/Documentation/core-api/
H A Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
[all …]
/openbmc/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
52 Please exit any audio application running before switching between bit depths
[all …]
/openbmc/linux/drivers/net/ethernet/microsoft/mana/
H A Dshm_channel.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
17 #define SHMEM_VF_RESET_STATE ((u32)-1)
38 * direction: 0 for request, VF->PF; 1 for response, PF->VF.
67 #define SMC_LAST_DWORD (SMC_APERTURE_DWORDS - 1)
75 /* Poll the hardware for the ownership bit. This should be pretty fast, in mana_smc_poll_register()
87 if (!(last_dword & BIT(31))) in mana_smc_poll_register()
93 return -ETIMEDOUT; in mana_smc_poll_register()
99 void __iomem *base = sc->base; in mana_smc_read_response()
116 dev_err(sc->dev, "Wrong SMC response 0x%x, type=%d, ver=%d\n", in mana_smc_read_response()
118 return -EPROTO; in mana_smc_read_response()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
8 #include <clk-uclass.h>
16 #include <dt-bindings/mfd/stm32f7-rcc.h>
18 #define RCC_CR_HSION BIT(0)
19 #define RCC_CR_HSEON BIT(16)
20 #define RCC_CR_HSERDY BIT(17)
21 #define RCC_CR_HSEBYP BIT(18)
22 #define RCC_CR_CSSON BIT(19)
23 #define RCC_CR_PLLON BIT(24)
[all …]
/openbmc/linux/arch/powerpc/kernel/vdso/
H A Dsigtramp32.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
23 .Lsig_start = . - 4
43 .uleb128 9f - 1f; /* length */ \
56 .uleb128 9f - 1f; /* length */ \
65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
72 .uleb128 9f - 1f; /* length */ \
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
102 .uleb128 9f - 1f; /* length */ \
105 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
H A Dsigtramp64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
48 .uleb128 9f - 1f; /* length */ \
61 .uleb128 9f - 1f; /* length */ \
70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
77 .uleb128 9f - 1f; /* length */ \
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
108 .uleb128 9f - 1f; /* length */ \
111 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dcrct10dif-pcl-asm_64.S2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
50 # /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
106 # bit order match the polynomial coefficient order.
136 # While >= 128 data bytes remain (not counting xmm0-7), fold the 128
137 # bytes xmm0-7 into them, storing the result back into xmm0-7.
147 # Now fold the 112 bytes in xmm0-xmm6 into the 16 bytes in xmm7.
167 add $128-16, len
200 movdqu -16(buf, len), %xmm1
203 # xmm2 = high order part of second chunk: xmm7 left-shifted by 'len' bytes.
209 # xmm7 = first chunk: xmm7 right-shifted by '16-len' bytes.
[all …]
/openbmc/qemu/ui/
H A Dvnc-enc-zywrle.h6 * GOVERNED BY A FOLLOWING BSD-STYLE SOURCE LICENSE. *
19 - Redistributions of source code must retain the above copyright
22 - Redistributions in binary form must reproduce the above copyright
26 - Neither the name of the Hitachi Systems & Services, Ltd. nor
49 /* Type A:lower bit omitting of EZW style. */
101 48, 48, 48, 48, 48, 48, 48, 48,
102 48, 48, 48, 56, 56, 56, 56, 56,
112 0, -120, -120, -120, -120, -120, -120, -120,
113 -120, -120, -120, -112, -112, -112, -112, -112,
114 -112, -112, -112, -112, -104, -104, -104, -104,
[all …]
/openbmc/linux/arch/mips/loongson64/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-direct.h>
9 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
10 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
18 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
19 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/openbmc/linux/arch/arm/crypto/
H A Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
166 // the bit order match the polynomial coefficient order.
167 vld1.64 {q0-q1}, [buf]!
168 vld1.64 {q2-q3}, [buf]!
169 vld1.64 {q4-q5}, [buf]!
[all …]
/openbmc/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
73 * [19:16] Playback mixer output enable. 1 bit per channel.
74 * [23:20] Capture mixer output enable. 1 bit per channel.
75 * [26:24] FX engine channel capture 0 = 0x60-0x67.
76 * 1 = 0x68-0x6f.
77 * 2 = 0x70-0x77.
78 * 3 = 0x78-0x7f.
[all …]
/openbmc/linux/include/sound/
H A Demu10k1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <sound/pcm-indirect.h>
25 /* ------------------- DEFINES -------------------- */
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
41 // This is used to define hardware bit-fields (sub-registers) by combining
42 // the bit shift and count with the actual register address. The passed
[all …]
/openbmc/linux/arch/alpha/kernel/
H A Dsys_wildfire.c1 // SPDX-License-Identifier: GPL-2.0
41 int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1); in wildfire_update_irq_hw()
42 int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1); in wildfire_update_irq_hw()
49 " got irq %d for non-existent PCA %d" in wildfire_update_irq_hw()
57 enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */ in wildfire_update_irq_hw()
72 enable0 = (unsigned long *) &pca->pca_int[0].enable; in wildfire_init_irq_hw()
73 enable1 = (unsigned long *) &pca->pca_int[1].enable; in wildfire_init_irq_hw()
74 enable2 = (unsigned long *) &pca->pca_int[2].enable; in wildfire_init_irq_hw()
75 enable3 = (unsigned long *) &pca->pca_int[3].enable; in wildfire_init_irq_hw()
77 target0 = (unsigned long *) &pca->pca_int[0].target; in wildfire_init_irq_hw()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_flat_memory.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
44 * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
57 * System Unified Address - SUA
81 * HSA64 - ATC/IOMMU 64b
86 * so the actual VA carried to translation is 48b. There is a “hole” in
106 * to a 49b address. This 49b address is constituted of an “ATC” bit
107 * plus a 48b virtual address. This 49b address is what is passed to the
108 * translation hardware. ATC==0 means the 48b address is a GPUVM address
110 * ATC==1 means the 48b address is intended to be translated via IOMMU
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylake/
H A Duncore-other.json3 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
7 "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwell/
H A Duncore-other.json3 "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",
7 "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
/openbmc/u-boot/include/
H A Data.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * "Information Technology - AT Attachment-3 Interface (ATA-3)"
11 * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
13 * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
22 * 8-bit (register) and 16-bit (data) accesses might use different
96 #define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */
97 #define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
98 #define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
101 #define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */
134 /* ------------------------------------------------------------------------- */
[all …]
/openbmc/u-boot/include/configs/
H A Dtam3517-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
47 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
48 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
124 CONFIG_SYS_INIT_RAM_SIZE - \
146 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
156 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
175 48, 49, 50, 51, 52, 53, 54, 55,\
199 "addip=if test -n ${ipdyn};then run addip_dyn;" \
223 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
224 "load=tftp ${loadaddr} ${u-boot}\0" \
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