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/openbmc/linux/arch/arm64/crypto/
H A Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
42 ld1 {v12.4s}, [x10]
45 // x0 += x1, x3 = rotl32(x3 ^ x0, 16)
46 add v0.4s, v0.4s, v1.4s
47 eor v3.16b, v3.16b, v0.16b
51 add v2.4s, v2.4s, v3.4s
[all …]
H A Dsm4-neon-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
35 ld1 {v16.16b-v19.16b}, [x5], #64; \
36 ld1 {v20.16b-v23.16b}, [x5], #64; \
37 ld1 {v24.16b-v27.16b}, [x5], #64; \
38 ld1 {v28.16b-v31.16b}, [x5];
41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
[all …]
H A Dsm4-ce-asm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 ld1 {v24.16b-v27.16b}, [ptr], #64; \
9 ld1 {v28.16b-v31.16b}, [ptr];
12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
[all …]
H A Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
19 .set .Lv\b\().4s, \b
37 * output: r0:r1 (low 128-bits in r0, high in r1)
40 ext T0.16b, m1.16b, m1.16b, #8; \
45 eor T0.16b, T0.16b, T1.16b; \
46 ext T1.16b, RZERO.16b, T0.16b, #8; \
47 ext T0.16b, T0.16b, RZERO.16b, #8; \
[all …]
H A Dsm3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
13 .set .Lv\b\().4s, \b
17 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
21 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
29 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
33 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
37 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
[all …]
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
40 .align 4
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
[all …]
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
14 ld1 {v1.4s}, [x0], #16
18 mov v3.16b, v1.16b
20 0: mov v2.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
[all …]
H A Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
19 .set .Lv\b\().4s, \b
27 .inst 0xce60c800 | (.L\vm << 16) | (.L\vn << 5) | .L\vd
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
[all …]
H A Dsha2-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
30 mov dg2v.16b, dg0v.16b
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
[all …]
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
21 sub w3, w3, #16
22 eor v1.16b, v1.16b, v1.16b
27 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
30 eor v0.16b, v0.16b, v1.16b
31 1: ld1 {v3.4s}, [x4] /* load first round key */
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/lib/
H A Dreg.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 #include <ppc-asm.h>
11 /* Non volatile GPR - unsigned long buf[18] */
15 ld 16, 2*8(3)
17 ld 18, 4*8(3)
29 ld 30, 16*8(3)
37 std 16, 2*8(3)
39 std 18, 4*8(3)
51 std 30, 16*8(3)
56 /* Double Precision Float - double buf[32] */
[all …]
/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
19 module_model_id 0x0000 16
23 - e GRBG 0
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dat-All1 # Austria, all DVB-T transmitters run by ORS
3 # http://www.ors.at/fileadmin/user_upload/downloads/DVB-T_Kanalbezeichnungen_und_Mittenfrequenzen.p…
8 CODE_RATE_HP = 3/4
10 MODULATION = QAM/16
12 GUARD_INTERVAL = 1/4
20 CODE_RATE_HP = 3/4
22 MODULATION = QAM/16
24 GUARD_INTERVAL = 1/4
32 CODE_RATE_HP = 3/4
34 MODULATION = QAM/16
[all …]
/openbmc/linux/arch/x86/crypto/
H A Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
23 #define kr (16*4)
24 #define rr ((16*4)+16)
26 /* s-boxes */
33 16-way AVX cast5
88 movl (RID2,RID1,4), dst ## d; \
91 op1 (RID1,RID2,4), dst ## d; \
[all …]
/openbmc/linux/arch/alpha/lib/
H A Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
55 bis $16,$16,$0 # E : return value
[all …]
H A Dcopy_user.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Notably, we have to make sure that $0 is always up-to-date and
21 .long 99b - .; \
22 lda $31, $exitin-99b($31); \
28 .long 99b - .; \
29 lda $31, $exitout-99b($31); \
33 .align 4
39 and $16,7,$3
43 .align 4
46 EXO( ldq_u $2,0($16) )
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 1. a += b; d ^= a; d <<<= 16;
17 # 4. c += d; b ^= c; b <<<= 7
19 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
24 # 4 blocks (a b c d)
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
55 li 16, \OFFSET
56 stvx \VRS, 16, \FRAME
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
14 # Block size 16 bytes
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
28 # setup r^4, r^3, r^2, r vectors
29 # vs [r^1, r^3, r^2, r^4]
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-timrot.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
14 #include <asm/mach-imx/regs-common.h>
60 #define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16)
61 #define TIMROT_ROTCTRL_DIVIDER_OFFSET 16
72 #define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4)
74 #define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4)
76 #define TIMROT_ROTCTRL_SELECT_B_OFFSET 4
77 #define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4)
78 #define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4)
[all …]
/openbmc/qemu/tests/unit/
H A Dtest-smp-parse.c2 * SMP parsing unit-tests
10 * See the COPYING.LIB file in the top-level directory.
26 #define SMP_MACHINE_NAME "TEST-SMP"
29 * Used to define the generic 3-level CPU topology hierarchy
30 * -sockets/cores/threads
51 * Currently a 5-level topology hierarchy is supported on PC machines
52 * -sockets/dies/modules/cores/threads
67 * Currently a 4-level topology hierarchy is supported on ARM virt machines
68 * -sockets/clusters/cores/threads
81 * Currently a 5-level topology hierarchy is supported on s390 ccw machines
[all …]
/openbmc/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga3d_surfacedefs.h2 * Copyright 2008-2021 VMware, Inc.
3 * SPDX-License-Identifier: GPL-2.0 OR MIT
28 * svga3d_surfacedefs.h --
71 SVGA3DBLOCKDESC_BUFFER = 1 << 4,
93 SVGA3DBLOCKDESC_SRGB = 1 << 16,
335 4,
336 4,
338 { { 0 }, { 8 }, { 16 }, { 24 } } },
343 4,
344 4,
[all …]
/openbmc/linux/arch/powerpc/lib/
H A Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
56 /* first check for a 4kB copy on a 4kB boundary */
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/copyloops/
H A Dcopyuser_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-compat.h>
9 #include <asm/feature-fixups.h>
17 #define sLd sld /* Shift towards low-numbered address. */
18 #define sHd srd /* Shift towards high-numbered address. */
20 #define sLd srd /* Shift towards low-numbered address. */
21 #define sHd sld /* Shift towards high-numbered address. */
39 100: EX_TABLE(100b, .Lld_exc - r3_offset)
43 100: EX_TABLE(100b, .Lst_exc - r3_offset)
56 /* first check for a 4kB copy on a 4kB boundary */
[all …]
/openbmc/u-boot/include/
H A Dflash.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2000-2005
14 /*-----------------------------------------------------------------------
45 const char *name; /* human-readable name */
50 #ifdef CONFIG_CFI_FLASH /* DM-specific parts */
120 /*-----------------------------------------------------------------------
126 #define ERR_PROTECTED 4
128 #define ERR_ALIGN 16
134 /*-----------------------------------------------------------------------
140 /*-----------------------------------------------------------------------
[all …]
/openbmc/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
14 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
26 * N/A 12G ~ 16G
28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
[all …]

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