1*2d555a38SYong Wu /* SPDX-License-Identifier: GPL-2.0-only */ 2*2d555a38SYong Wu /* 3*2d555a38SYong Wu * Copyright (c) 2022 MediaTek Inc. 4*2d555a38SYong Wu * 5*2d555a38SYong Wu * Author: Anan Sun <anan.sun@mediatek.com> 6*2d555a38SYong Wu * Author: Yong Wu <yong.wu@mediatek.com> 7*2d555a38SYong Wu */ 8*2d555a38SYong Wu #ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ 9*2d555a38SYong Wu #define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_ 10*2d555a38SYong Wu 11*2d555a38SYong Wu #include <dt-bindings/memory/mtk-memory-port.h> 12*2d555a38SYong Wu 13*2d555a38SYong Wu /* 14*2d555a38SYong Wu * MM IOMMU supports 16GB dma address. We separate it to four ranges: 15*2d555a38SYong Wu * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 16*2d555a38SYong Wu * locate in anyone region. BUT: 17*2d555a38SYong Wu * a) Make sure all the ports inside a larb are in one range. 18*2d555a38SYong Wu * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 19*2d555a38SYong Wu * 20*2d555a38SYong Wu * This is the suggested mapping in this SoC: 21*2d555a38SYong Wu * 22*2d555a38SYong Wu * modules dma-address-region larbs-ports 23*2d555a38SYong Wu * disp 0 ~ 4G larb0/1/2 24*2d555a38SYong Wu * vcodec 4G ~ 8G larb4/7 25*2d555a38SYong Wu * cam/mdp 8G ~ 12G the other larbs. 26*2d555a38SYong Wu * N/A 12G ~ 16G 27*2d555a38SYong Wu * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10 28*2d555a38SYong Wu * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5 29*2d555a38SYong Wu */ 30*2d555a38SYong Wu 31*2d555a38SYong Wu /* MM IOMMU ports */ 32*2d555a38SYong Wu /* LARB 0 -- MMSYS */ 33*2d555a38SYong Wu #define IOMMU_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) 34*2d555a38SYong Wu #define IOMMU_PORT_L0_REVERSED MTK_M4U_ID(0, 1) 35*2d555a38SYong Wu #define IOMMU_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2) 36*2d555a38SYong Wu #define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3) 37*2d555a38SYong Wu 38*2d555a38SYong Wu /* LARB 1 -- MMSYS */ 39*2d555a38SYong Wu #define IOMMU_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 0) 40*2d555a38SYong Wu #define IOMMU_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 1) 41*2d555a38SYong Wu #define IOMMU_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 2) 42*2d555a38SYong Wu #define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3) 43*2d555a38SYong Wu #define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4) 44*2d555a38SYong Wu 45*2d555a38SYong Wu /* LARB 2 -- MMSYS */ 46*2d555a38SYong Wu #define IOMMU_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) 47*2d555a38SYong Wu #define IOMMU_PORT_L2_MDP_RDMA1 MTK_M4U_ID(2, 1) 48*2d555a38SYong Wu #define IOMMU_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) 49*2d555a38SYong Wu #define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3) 50*2d555a38SYong Wu #define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4) 51*2d555a38SYong Wu 52*2d555a38SYong Wu /* LARB 4 -- VDEC */ 53*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0) 54*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1) 55*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2) 56*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3) 57*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4) 58*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5) 59*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6) 60*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7) 61*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8) 62*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9) 63*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10) 64*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11) 65*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12) 66*2d555a38SYong Wu #define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13) 67*2d555a38SYong Wu 68*2d555a38SYong Wu /* LARB 7 -- VENC */ 69*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_RCPU MTK_M4U_ID(7, 0) 70*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_REC MTK_M4U_ID(7, 1) 71*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_BSDMA MTK_M4U_ID(7, 2) 72*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_SV_COMV MTK_M4U_ID(7, 3) 73*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4) 74*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_CUR_LUMA MTK_M4U_ID(7, 5) 75*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_CUR_CHROMA MTK_M4U_ID(7, 6) 76*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_REF_LUMA MTK_M4U_ID(7, 7) 77*2d555a38SYong Wu #define IOMMU_PORT_L7_VENC_REF_CHROMA MTK_M4U_ID(7, 8) 78*2d555a38SYong Wu #define IOMMU_PORT_L7_JPGENC_Y_RDMA MTK_M4U_ID(7, 9) 79*2d555a38SYong Wu #define IOMMU_PORT_L7_JPGENC_C_RDMA MTK_M4U_ID(7, 10) 80*2d555a38SYong Wu #define IOMMU_PORT_L7_JPGENC_Q_TABLE MTK_M4U_ID(7, 11) 81*2d555a38SYong Wu #define IOMMU_PORT_L7_JPGENC_BSDMA MTK_M4U_ID(7, 12) 82*2d555a38SYong Wu 83*2d555a38SYong Wu /* LARB 8 -- WPE */ 84*2d555a38SYong Wu #define IOMMU_PORT_L8_WPE_RDMA_0 MTK_M4U_ID(8, 0) 85*2d555a38SYong Wu #define IOMMU_PORT_L8_WPE_RDMA_1 MTK_M4U_ID(8, 1) 86*2d555a38SYong Wu #define IOMMU_PORT_L8_WPE_WDMA_0 MTK_M4U_ID(8, 2) 87*2d555a38SYong Wu 88*2d555a38SYong Wu /* LARB 9 -- IMG-1 */ 89*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_IMGI_D1 MTK_M4U_ID(9, 0) 90*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_IMGBI_D1 MTK_M4U_ID(9, 1) 91*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_DMGI_D1 MTK_M4U_ID(9, 2) 92*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_DEPI_D1 MTK_M4U_ID(9, 3) 93*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4) 94*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_SMTI_D1 MTK_M4U_ID(9, 5) 95*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_SMTO_D2 MTK_M4U_ID(9, 6) 96*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_SMTO_D1 MTK_M4U_ID(9, 7) 97*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_CRZO_D1 MTK_M4U_ID(9, 8) 98*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_IMG3O_D1 MTK_M4U_ID(9, 9) 99*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_VIPI_D1 MTK_M4U_ID(9, 10) 100*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_SMTI_D5 MTK_M4U_ID(9, 11) 101*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_TIMGO_D1 MTK_M4U_ID(9, 12) 102*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_UFBC_W0 MTK_M4U_ID(9, 13) 103*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_UFBC_R0 MTK_M4U_ID(9, 14) 104*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_WPE_RDMA1 MTK_M4U_ID(9, 15) 105*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16) 106*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_WPE_WDMA MTK_M4U_ID(9, 17) 107*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA0 MTK_M4U_ID(9, 18) 108*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA1 MTK_M4U_ID(9, 19) 109*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA2 MTK_M4U_ID(9, 20) 110*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA3 MTK_M4U_ID(9, 21) 111*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA4 MTK_M4U_ID(9, 22) 112*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_RDMA5 MTK_M4U_ID(9, 23) 113*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_WDMA0 MTK_M4U_ID(9, 24) 114*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_MFB_WDMA1 MTK_M4U_ID(9, 25) 115*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_RESERVE6 MTK_M4U_ID(9, 26) 116*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_RESERVE7 MTK_M4U_ID(9, 27) 117*2d555a38SYong Wu #define IOMMU_PORT_L9_IMG_RESERVE8 MTK_M4U_ID(9, 28) 118*2d555a38SYong Wu 119*2d555a38SYong Wu /* LARB 11 -- IMG-2 */ 120*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_IMGI_D1 MTK_M4U_ID(11, 0) 121*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_IMGBI_D1 MTK_M4U_ID(11, 1) 122*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_DMGI_D1 MTK_M4U_ID(11, 2) 123*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_DEPI_D1 MTK_M4U_ID(11, 3) 124*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4) 125*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_SMTI_D1 MTK_M4U_ID(11, 5) 126*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_SMTO_D2 MTK_M4U_ID(11, 6) 127*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_SMTO_D1 MTK_M4U_ID(11, 7) 128*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_CRZO_D1 MTK_M4U_ID(11, 8) 129*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_IMG3O_D1 MTK_M4U_ID(11, 9) 130*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_VIPI_D1 MTK_M4U_ID(11, 10) 131*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_SMTI_D5 MTK_M4U_ID(11, 11) 132*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_TIMGO_D1 MTK_M4U_ID(11, 12) 133*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_UFBC_W0 MTK_M4U_ID(11, 13) 134*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_UFBC_R0 MTK_M4U_ID(11, 14) 135*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_WPE_RDMA1 MTK_M4U_ID(11, 15) 136*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16) 137*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_WPE_WDMA MTK_M4U_ID(11, 17) 138*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA0 MTK_M4U_ID(11, 18) 139*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA1 MTK_M4U_ID(11, 19) 140*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA2 MTK_M4U_ID(11, 20) 141*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA3 MTK_M4U_ID(11, 21) 142*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA4 MTK_M4U_ID(11, 22) 143*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_RDMA5 MTK_M4U_ID(11, 23) 144*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_WDMA0 MTK_M4U_ID(11, 24) 145*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_MFB_WDMA1 MTK_M4U_ID(11, 25) 146*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_RESERVE6 MTK_M4U_ID(11, 26) 147*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_RESERVE7 MTK_M4U_ID(11, 27) 148*2d555a38SYong Wu #define IOMMU_PORT_L11_IMG_RESERVE8 MTK_M4U_ID(11, 28) 149*2d555a38SYong Wu 150*2d555a38SYong Wu /* LARB 13 -- CAM */ 151*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_MRAWI MTK_M4U_ID(13, 0) 152*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_MRAWO_0 MTK_M4U_ID(13, 1) 153*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_MRAWO_1 MTK_M4U_ID(13, 2) 154*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_CAMSV_4 MTK_M4U_ID(13, 6) 155*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_CAMSV_5 MTK_M4U_ID(13, 7) 156*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_CAMSV_6 MTK_M4U_ID(13, 8) 157*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_CCUI MTK_M4U_ID(13, 9) 158*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_CCUO MTK_M4U_ID(13, 10) 159*2d555a38SYong Wu #define IOMMU_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 11) 160*2d555a38SYong Wu 161*2d555a38SYong Wu /* LARB 14 -- CAM */ 162*2d555a38SYong Wu #define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4) 163*2d555a38SYong Wu #define IOMMU_PORT_L14_CAM_CCUO MTK_M4U_ID(14, 5) 164*2d555a38SYong Wu 165*2d555a38SYong Wu /* LARB 16 -- RAW-A */ 166*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0) 167*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1) 168*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2) 169*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3) 170*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4) 171*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5) 172*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6) 173*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7) 174*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8) 175*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9) 176*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10) 177*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11) 178*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12) 179*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13) 180*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14) 181*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15) 182*2d555a38SYong Wu #define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16) 183*2d555a38SYong Wu 184*2d555a38SYong Wu /* LARB 17 -- RAW-B */ 185*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_IMGO_R1_B MTK_M4U_ID(17, 0) 186*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_RRZO_R1_B MTK_M4U_ID(17, 1) 187*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_CQI_R1_B MTK_M4U_ID(17, 2) 188*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_BPCI_R1_B MTK_M4U_ID(17, 3) 189*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4) 190*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_UFDI_R2_B MTK_M4U_ID(17, 5) 191*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_RAWI_R2_B MTK_M4U_ID(17, 6) 192*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_RAWI_R3_B MTK_M4U_ID(17, 7) 193*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_AAO_R1_B MTK_M4U_ID(17, 8) 194*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_AFO_R1_B MTK_M4U_ID(17, 9) 195*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_FLKO_R1_B MTK_M4U_ID(17, 10) 196*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_LCESO_R1_B MTK_M4U_ID(17, 11) 197*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_CRZO_R1_B MTK_M4U_ID(17, 12) 198*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_LTMSO_R1_B MTK_M4U_ID(17, 13) 199*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_RSSO_R1_B MTK_M4U_ID(17, 14) 200*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_AAHO_R1_B MTK_M4U_ID(17, 15) 201*2d555a38SYong Wu #define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16) 202*2d555a38SYong Wu 203*2d555a38SYong Wu /* LARB 19 -- IPE */ 204*2d555a38SYong Wu #define IOMMU_PORT_L19_IPE_DVS_RDMA MTK_M4U_ID(19, 0) 205*2d555a38SYong Wu #define IOMMU_PORT_L19_IPE_DVS_WDMA MTK_M4U_ID(19, 1) 206*2d555a38SYong Wu #define IOMMU_PORT_L19_IPE_DVP_RDMA MTK_M4U_ID(19, 2) 207*2d555a38SYong Wu #define IOMMU_PORT_L19_IPE_DVP_WDMA MTK_M4U_ID(19, 3) 208*2d555a38SYong Wu 209*2d555a38SYong Wu /* LARB 20 -- IPE */ 210*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_FDVT_RDA MTK_M4U_ID(20, 0) 211*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_FDVT_RDB MTK_M4U_ID(20, 1) 212*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_FDVT_WRA MTK_M4U_ID(20, 2) 213*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_FDVT_WRB MTK_M4U_ID(20, 3) 214*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4) 215*2d555a38SYong Wu #define IOMMU_PORT_L20_IPE_RSC_WDMA MTK_M4U_ID(20, 5) 216*2d555a38SYong Wu 217*2d555a38SYong Wu #endif 218