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/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h63 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
74 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
239 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
240 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
241 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
242 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) argument
243 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) argument
244 #define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16)) argument
245 #define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16)) argument
246 #define GLTSYN_EVNT_H_IDX_MAX 3
[all …]
/openbmc/linux/sound/pci/hda/
H A Dca0132_regs.h33 #define XRAM_XRAM_INST_OFFSET(_chan) \ argument
35 (_chan * XRAM_XRAM_CHAN_INCR))
41 #define YRAM_YRAM_INST_OFFSET(_chan) \ argument
43 (_chan * YRAM_YRAM_CHAN_INCR))
49 #define UC_UC_INST_OFFSET(_chan) \ argument
51 (_chan * UC_UC_CHAN_INCR))
57 #define AXRAM_AXRAM_INST_OFFSET(_chan) \ argument
59 (_chan * AXRAM_AXRAM_CHAN_INCR))
65 #define AYRAM_AYRAM_INST_OFFSET(_chan) \ argument
67 (_chan * AYRAM_AYRAM_CHAN_INCR))
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/openbmc/linux/drivers/iio/adc/
H A Dltc2497-core.c20 #define LTC2497_SIGN BIT(3)
108 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
111 .channel = (_chan), \
112 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
118 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
121 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
122 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
123 .address = (_addr | _chan), \
133 LTC2497_CHAN(3, LTC2497_SGL, "CH3"),
149 LTC2497_CHAN_DIFF(3, LTC2497_DIFF),
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H A Dad7266.c31 struct spi_transfer single_xfer[3];
37 struct gpio_desc *gpios[3];
117 for (i = 0; i < 3; ++i) in ad7266_select_input()
189 #define AD7266_CHAN(_chan, _sign) { \ argument
192 .channel = (_chan), \
193 .address = (_chan), \
197 .scan_index = (_chan), \
212 AD7266_CHAN(3, (_sign)), \
236 #define AD7266_CHAN_DIFF(_chan, _sign) { \ argument
239 .channel = (_chan) * 2, \
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H A Dmeson_saradc.c42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ argument
50 (GENMASK(2, 0) << ((_chan) * 3))
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ argument
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ argument
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ argument
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ argument
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H A Dxilinx-xadc-core.c380 if (div <= 3) in xadc_zynq_setup()
526 events |= (status & 0x0001) << 3; in xadc_axi_interrupt_handler()
547 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | in xadc_axi_update_alarm()
1057 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \ argument
1060 .channel = (_chan), \
1078 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \ argument
1081 .channel = (_chan), \
1100 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \ argument
1101 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1102 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \ argument
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H A Dti-ads1015.c43 #define ADS1015_CFG_COMP_POL_SHIFT 3
52 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
60 #define ADS1015_CFG_COMP_DISABLE 3
182 #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \ argument
186 .channel = _chan, \
203 .datasheet_name = "AIN"#_chan, \
206 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs)… argument
211 .channel = _chan, \
229 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
320 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4,
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H A Dti-ads7924.c122 #define ADS7924_V_CHAN(_chan, _addr) { \ argument
125 .channel = _chan, \
129 .datasheet_name = "AIN"#_chan, \
189 ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG),
H A Dad7292.c42 #define AD7292_VOLTAGE_CHAN(_chan) \ argument
48 .channel = _chan, \
55 AD7292_VOLTAGE_CHAN(3),
72 AD7292_VOLTAGE_CHAN(3),
H A Dad7291.c40 #define AD7291_DATA_HIGH(x) ((x) * 3 + 0x4)
41 #define AD7291_DATA_LOW(x) ((x) * 3 + 0x5)
42 #define AD7291_HYST(x) ((x) * 3 + 0x6)
56 #define AD7291_ALERT_POLARITY BIT(3)
74 #define AD7291_T_AVG_HIGH BIT(3)
423 #define AD7291_VOLTAGE_CHAN(_chan) \ argument
429 .channel = _chan, \
438 AD7291_VOLTAGE_CHAN(3),
H A Dad9467.c149 unsigned char buf[3]; in ad9467_spi_write()
211 #define AD9467_CHAN(_chan, _si, _bits, _sign) \ argument
215 .channel = _chan, \
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c37 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
44 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \ argument
45 (GENMASK(2, 0) << ((_chan) * 3))
48 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \ argument
49 (16 + ((_chan) * 2))
50 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \ argument
51 (GENMASK(17, 16) << ((_chan) * 2))
52 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \ argument
53 (0 + ((_chan) * 2))
54 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \ argument
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dtsc2007_iio.c15 #define TSC2007_CHAN_IIO(_chan, _name, _type, _chan_info) \ argument
22 .channel = _chan, \
29 TSC2007_CHAN_IIO(3, "z2", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
64 case 3: in tsc2007_read_raw()
/openbmc/linux/drivers/iio/dac/
H A Dad5624r_spi.c29 u8 msg[3]; in ad5624r_spi_write()
34 * followed by the 3-bit DAC address, A2 to A0, and then the in ad5624r_spi_write()
166 #define AD5624R_CHANNEL(_chan, _bits) { \ argument
170 .channel = (_chan), \
173 .address = (_chan), \
188 AD5624R_CHANNEL(3, _bits), \
H A Dad5764.c25 #define AD5764_REG_DATA(x) ((2 << 3) | (x))
26 #define AD5764_REG_COARSE_GAIN(x) ((3 << 3) | (x))
27 #define AD5764_REG_FINE_GAIN(x) ((4 << 3) | (x))
28 #define AD5764_REG_OFFSET(x) ((5 << 3) | (x))
75 #define AD5764_CHANNEL(_chan, _bits) { \ argument
79 .channel = (_chan), \
80 .address = (_chan), \
99 AD5764_CHANNEL(3, (_bits)), \
133 ret = spi_write(st->spi, &st->data[0].d8[1], 3); in ad5764_write()
147 .len = 3, in ad5764_read()
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H A Dad5504.c248 #define AD5504_CHANNEL(_chan) { \ argument
252 .channel = (_chan), \
255 .address = AD5504_ADDR_DAC(_chan), \
268 AD5504_CHANNEL(3),
H A Dad5766.c32 #define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
33 #define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
39 #define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
109 * 3: 0.25 SCALING.
126 } data[3] __aligned(IIO_DMA_MINALIGN);
152 .len = 3, in __ad5766_spi_read()
158 .len = 3, in __ad5766_spi_read()
179 return spi_write(st->spi, &st->data[0].b8[0], 3); in __ad5766_spi_write()
443 #define AD576x_CHANNEL(_chan, _bits) { \ argument
447 .channel = (_chan), \
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H A Dltc2632.c78 u8 msg[3]; in ltc2632_spi_write()
184 #define LTC2632_CHANNEL(_chan, _bits) { \ argument
188 .channel = (_chan), \
191 .address = (_chan), \
204 LTC2632_CHANNEL(3, _bits), \
/openbmc/linux/drivers/iio/cdc/
H A Dad7150.c25 #define AD7150_STATUS_OUT1 BIT(3)
28 #define AD7150_CH2_DATA_HIGH_REG 3
34 #define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
71 * 3:0 are for timeout receding - applies if below lower threshold
201 ad7150_addresses[chan][3], in ad7150_write_event_params()
437 #define AD7150_CAPACITANCE_CHAN(_chan) { \ argument
440 .channel = _chan, \
450 #define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \ argument
453 .channel = _chan, \
/openbmc/linux/drivers/comedi/drivers/
H A Ddas6402.c45 #define DAS6402_STATUS_XINT BIT(3)
62 #define DAS6402_CTRL_PACER_TRIG DAS6402_CTRL_TRIG(3)
64 #define DAS6402_CTRL_XINTE BIT(3)
71 #define DAS6402_TRIG_PRETRIG BIT(3)
72 #define DAS6402_AO_RANGE(_chan, _range) ((_range) << ((_chan) ? 6 : 4)) argument
73 #define DAS6402_AO_RANGE_MASK(_chan) (3 << ((_chan) ? 6 : 4)) argument
79 #define DAS6402_MODE_EOB DAS6402_MODE_RANGE(3)
314 /* Step 3: check if arguments are trivially valid */ in das6402_ai_cmdtest()
329 return 3; in das6402_ai_cmdtest()
569 /* IRQs 2,3,5,6,7, 10,11,15 are valid for "enhanced" mode */ in das6402_attach()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-pktdma.yaml169 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
/openbmc/ipmitool/include/ipmitool/
H A Dipmi_sdr.h88 #define SDR_SENSOR_STAT_HI_NC (1<<3)
128 unsigned char popChangeInd[3]; /* free space in SDR */
387 uint8_t rate:3;
393 uint8_t rate:3;
405 #define UNITS_ARE_DISCRETE(s) ((s)->unit.analog == 3)
442 uint8_t __reserved[3];
585 uint8_t pwr_state_notif:3;
591 uint8_t pwr_state_notif:3;
594 uint8_t __reserved4[3];
611 uint8_t bus:3;
[all …]
/openbmc/linux/drivers/dma/
H A Dfsl-edma-main.c102 struct dma_chan *chan, *_chan; in fsl_edma_xlate() local
111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
135 struct dma_chan *chan, *_chan; in fsl_edma3_xlate() local
140 if (dma_spec->args_count != 3) in fsl_edma3_xlate()
146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
H A Dat_hdmac.c156 #define ATC_SRC_PER GENMASK(3, 0) /* Channel src rq associated with periph handshaking ifc h */
297 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3, 32 -> 4, 64 -> 5, 128 -> 6, 256 -> 7.
528 if (!((src | dst | len) & 3)) in atc_get_xfer_width()
1308 if (unlikely(mem & 3 || len & 3)) in atc_prep_slave_sg()
1357 if (unlikely(mem & 3 || len & 3)) in atc_prep_slave_sg()
2106 struct dma_chan *chan, *_chan; in at_dma_remove() local
2117 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, in at_dma_remove()
2140 struct dma_chan *chan, *_chan; in at_dma_prepare() local
2142 list_for_each_entry_safe(chan, _chan, &atdma->dma_device.channels, in at_dma_prepare()
2174 struct dma_chan *chan, *_chan; in at_dma_suspend_noirq() local
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H A Dat_xdmac.c66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
107 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
173 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
424 struct dma_chan *chan, *_chan; at_xdmac_off() local
2132 struct dma_chan *chan, *_chan; atmel_xdmac_prepare() local
2147 struct dma_chan *chan, *_chan; atmel_xdmac_suspend() local
2185 struct dma_chan *chan, *_chan; atmel_xdmac_resume() local
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