iio/dac/ad5766.c

32 #define AD5766_CMD_WR_IN_REG(x)			(0x10 | ((x) & GENMASK(3, 0)))
33 #define AD5766_CMD_WR_DAC_REG(x)		(0x20 | ((x) & GENMASK(3, 0)))
39 #define AD5766_CMD_READBACK_REG(x)		(0x80 | ((x) & GENMASK(3, 0)))
109  *			3: 0.25 SCALING.
126 	} data[3] __aligned(IIO_DMA_MINALIGN);
152 			.len = 3,  in __ad5766_spi_read()
158 			.len = 3,  in __ad5766_spi_read()
179 	return spi_write(st->spi, &st->data[0].b8[0], 3);  in __ad5766_spi_write()
443 #define AD576x_CHANNEL(_chan, _bits) {					\  argument
447 	.channel = (_chan),						\
448 	.address = (_chan),						\
452 	.scan_index = (_chan),						\
467 	AD576x_CHANNEL(3, (_bits)),				\