drivers/dma/at_xdmac.c

66 #define		AT_XDMAC_CIE_FIE	BIT(3)	/* End of Flush Interrupt Enable Bit */
74 #define		AT_XDMAC_CID_FID	BIT(3)	/* End of Flush Interrupt Disable Bit */
82 #define		AT_XDMAC_CIM_FIM	BIT(3)	/* End of Flush Interrupt Mask Bit */
90 #define		AT_XDMAC_CIS_FIS	BIT(3)	/* End of Flush Interrupt Status Bit */
104 #define		AT_XDMAC_CNDC_NDVIEW_NDV0	(0x0 << 3)		/* Channel x Next Descriptor View 0 */
105 #define		AT_XDMAC_CNDC_NDVIEW_NDV1	(0x1 << 3)		/* Channel x Next Descriptor View 1 */
106 #define		AT_XDMAC_CNDC_NDVIEW_NDV2	(0x2 << 3)		/* Channel x Next Descriptor View 2 */
107 #define		AT_XDMAC_CNDC_NDVIEW_NDV3	(0x3 << 3)		/* Channel x Next Descriptor View 3 */
173 #define AT_XDMAC_MBR_UBC_NDV3		(0x3 << 27)	/* Next Descriptor View 3 */
424 	struct dma_chan		*chan, *_chan;
442 		list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels,
963 	} else if (!(addr & 3)) {
2134 	struct dma_chan		*chan, *_chan;
2136 	list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2149 	struct dma_chan		*chan, *_chan;
2156 	list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2187 	struct dma_chan		*chan, *_chan;
2207 	list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {