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/openbmc/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
11 - 32/64/128/256 BTB.
23 - 32/64/128-entry 4-way set-associati.ve main TLB.
27 - 4KB & 1MB.
28 - 8KB & 1MB.
33 - Cache size: 8KB/16KB/32KB/64KB.
34 - Cache line size: 16B/32B.
38 - Size: 4KB to 1MB.
H A DREADME.b4860qds45 . 32 Kbyte L1 ICache per e6500/SC3900 core
46 . 32 Kbyte L1 DCache per e6500/SC3900 core
61 . 182 32-bit timers
90 - 2 KB internal memory space including
173 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
175 0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
179 0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
180 0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
181 0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
188 0xF_0000_0000 0xF_01FF_FFFF DCSR 32 MB
[all …]
H A DREADME.rockchip210 The bootrom of rk3188 expects to find a small 1kb loader which returns
212 can then be up to 29kb in size and does the regular ddr init. This is
219 and decodes 2kb pages, so files should be sized accordingly.
267 header and skipping every second 2KB block. Then the U-Boot image is written at
268 offset 128KB and the whole image is padded to 4MB which is the SPI flash size.
279 U-Boot SPL 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32)
282 U-Boot 2015.07-rc2-00215-g9a58220-dirty (Jun 23 2015 - 12:11:32 -0600)
329 rksd.c produces an image consisting of 32KB of empty space, a header and
338 The maximum size of u-boot-spl-dtb.bin which the boot ROM will read is 32KB,
354 resulting image is then spread out so that only the first 2KB of each 4KB
[all …]
/openbmc/linux/arch/sh/mm/
H A DKconfig35 The page size is not necessarily 4KB. Keep this in mind when
69 def_bool !32BIT
72 config 32BIT
77 bool "Support 32-bit physical addressing through PMB"
79 select 32BIT
83 32-bits through the SH-4A PMB. If this is not set, legacy
155 bool "4kB"
160 bool "8kB"
163 This enables 8kB pages as supported by SH-X2 and later MMUs.
166 bool "16kB"
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME14 - two e5500 cores, each with a private 256 KB L2 cache
19 - 256 KB shared L3 CoreNet platform cache (CPC)
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
57 - 32-bit RISC controller for flexible support of the communications peripherals
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
107 - SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
129 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
130 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
132 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
[all …]
/openbmc/linux/Documentation/admin-guide/cgroup-v1/
H A Dhugetlb.rst34 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
46 hugetlb.64KB.limit_in_bytes
47 hugetlb.64KB.max_usage_in_bytes
48 hugetlb.64KB.numa_stat
49 hugetlb.64KB.usage_in_bytes
50 hugetlb.64KB.failcnt
51 hugetlb.64KB.rsvd.limit_in_bytes
52 hugetlb.64KB.rsvd.max_usage_in_bytes
53 hugetlb.64KB.rsvd.usage_in_bytes
54 hugetlb.64KB.rsvd.failcnt
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME14 - two e5500 cores, each with a private 256 KB L2 cache
19 - 256 KB shared L3 CoreNet platform cache (CPC)
24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
57 - 32-bit RISC controller for flexible support of the communications peripherals
71 DDR: 64-bit 32-bit
72 IFC: 32-bit 28-bit
155 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
156 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
158 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
159 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
[all …]
/openbmc/u-boot/board/freescale/t1040qds/
H A DREADME14 - Four e5500 cores, each with a private 256 KB L2 cache
15 - 256 KB shared L3 CoreNet platform cache (CPC)
17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
99 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
100 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
102 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
103 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
104 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
105 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
106 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
[all …]
/openbmc/linux/arch/parisc/
H A DKconfig187 that can run on all 32-bit PA CPUs (albeit not optimally fast),
269 and slower than the 32bit one.
276 bool "4KB"
279 performance, a page size of 16KB is recommended. For best
280 compatibility with 32bit applications, a page size of 4KB should be
281 selected (the vast majority of 32bit binaries work perfectly fine
284 4KB For best 32bit compatibility
285 16KB For best performance
286 64KB For best performance, might give more overhead.
288 If you don't know what to do, choose 4KB.
[all …]
/openbmc/u-boot/board/freescale/t4qds/
H A DREADME10 32 lanes grouped into four 8-lane banks
45 - Support for 32-bit devices
108 0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
109 0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
110 0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
111 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
114 0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
115 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
147 and copy U-Boot(768 KB) from NAND/SD device to DDR.
158 |SecureBoot header | 0xFFFC0000 (32KB) |
[all …]
/openbmc/linux/arch/ia64/
H A DKconfig73 the 32-bit X86 line. The IA-64 Linux project has a home
145 bool "4KB"
148 performance, a page size of 8KB or 16KB is recommended. For best
149 IA-32 compatibility, a page size of 4KB should be selected (the vast
150 majority of IA-32 binaries work perfectly fine with a larger page
151 size). For Itanium 2 or newer systems, a page size of 64KB can also
154 4KB For best IA-32 compatibility
155 8KB For best IA-64 performance
156 16KB For best IA-64 performance
157 64KB Requires Itanium 2 or newer processor.
[all …]
/openbmc/u-boot/arch/x86/
H A DKconfig8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
26 supported normal setup. U-Boot will stay in 32-bit mode even on
39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
41 runs through the 16-bit and 32-bit init, then switches to 64-bit
158 # The following options control where the 16-bit and 32-bit init lies
[all …]
/openbmc/u-boot/board/freescale/t208xrdb/
H A DREADME13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
89 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
90 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
92 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
93 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
94 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
95 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
96 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
97 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
[all …]
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME46 0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
47 0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
49 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
50 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
55 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
56 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
57 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
67 0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
68 0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
/openbmc/linux/arch/powerpc/lib/
H A Dtest-code-patching.c68 /* Largest negative relative branch, - 32 MB */ in test_branch_iform()
87 /* Maximum relative negative offset, - 32 MB */ in test_branch_iform()
92 /* Out of range relative negative offset, - 32 MB + 4*/ in test_branch_iform()
96 /* Out of range relative positive offset, + 32 MB */ in test_branch_iform()
151 /* Maximum positive relative conditional branch, + 32 KB - 4B */ in test_branch_bform()
157 /* Largest negative relative conditional branch, - 32 KB */ in test_branch_bform()
179 /* Maximum relative negative offset, - 32 KB */ in test_branch_bform()
184 /* Out of range relative negative offset, - 32 KB + 4*/ in test_branch_bform()
188 /* Out of range relative positive offset, + 32 KB */ in test_branch_bform()
226 /* Maximum negative case, move b . to addr + 32 MB */ in test_translate_branch()
[all …]
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME45 - Four e5500 cores, each with a private 256 KB L2 cache
46 - 256 KB shared L3 CoreNet platform cache (CPC)
48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
168 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
169 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
171 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
172 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
173 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
174 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
175 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
69 - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
124 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
125 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
127 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
128 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
129 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
130 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
131 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_gfx_if.h74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
125 …ddr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
126 …uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binar…
128 …f_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
129 …uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
130 …_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
151 …uf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
152 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
153 …uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bi…
166 …e; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
[all …]
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dlaw.c22 *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
23 *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
24 *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
25 *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dlaw.c24 *6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
25 *6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
26 *6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
27 *6.e) 0xfe00_0000 0xffff_ffff Flash 32MB
/openbmc/qemu/tests/qemu-iotests/
H A D125100 # With a cluster size of 512 B, one L2 table covers 64 * 512 B = 32 kB.
101 # One cluster of the L1 table covers 64 * 32 kB = 2 MB.
106 # Therefore, we create an image that is 48 kB below 2 MB. Then:
107 # (1) We resize it to 2 MB - 32 kB. (+ 16 kB)
108 # (2) We resize it to 2 MB. (+ 48 kB)
109 # (3) We resize it to 2 MB + 32 kB. (+ 80 kB)
116 # in kB
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME50 0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
51 0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
54 0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
55 0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB
60 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
61 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
62 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
/openbmc/qemu/block/
H A Dvhdx.h28 * each block is 64KB:
31 * | File Id. | Header 1 | Header 2 | Region Table | Reserved (768KB) |
34 * 0.........64KB...........128KB........192KB..........256KB................1MB
88 the header is the first 4KB of the 64KB
91 /* The full header is 4KB, although the actual header data is much smaller.
92 * But for the checksum calculation, it is over the entire 4KB structure,
97 uint32_t checksum; /* CRC-32C hash of the whole header */
138 uint32_t checksum; /* CRC-32C hash of the 64KB table */
168 uint32_t checksum; /* CRC-32C hash of the 64KB table */
187 #define VHDX_LOG_DESC_SIZE 32
[all …]
/openbmc/linux/drivers/s390/crypto/
H A Dzcrypt_ep11misc.c118 static int ep11_kb_split(const u8 *kb, size_t kblen, u32 kbver, in ep11_kb_split() argument
129 hdr = (struct ep11kblob_header *)kb; in ep11_kb_split()
146 pl = (u8 *)kb + hdrsize; in ep11_kb_split()
162 static int ep11_kb_decode(const u8 *kb, size_t kblen, in ep11_kb_decode() argument
174 tmph = (struct ep11kblob_header *)kb; in ep11_kb_decode()
180 if (ep11_kb_split(kb, kblen, tmph->version, in ep11_kb_decode()
213 struct ep11keyblob *kb; in ep11_kb_wkvp() local
215 if (ep11_kb_decode(keyblob, keybloblen, NULL, NULL, &kb, NULL)) in ep11_kb_wkvp()
217 return kb->wkvp; in ep11_kb_wkvp()
228 struct ep11keyblob *kb = (struct ep11keyblob *)(key + sizeof(*hdr)); in ep11_check_aes_key_with_hdr() local
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/
H A D0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch35 * partition size: 176 KB
39 - * partition size: 512 KB
48 -/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
55 #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */
60 -/* The last 512KB of the SRAM is allocated as shared memory */
75 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
76 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

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