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/openbmc/qemu/include/libdecnumber/
H A DdecDPD.h42 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
43 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
48 /* uint8_t DPD2BCD8[4096]; -- DPD -> bytes (x3FF => 9 9 9 3) */
66 const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
261 const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
346 const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
429 const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
775 '\0','0','0','0', '\1','0','0','1', '\1','0','0','2', '\1','0','0','3', '\1','0','0','4',
777 '\2','0','1','0', '\2','0','1','1', '\2','0','1','2', '\2','0','1','3', '\2','0','1','4',
779 '\2','0','2','0', '\2','0','2','1', '\2','0','2','2', '\2','0','2','3', '\2','0','2','4',
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie.h102 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
105 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
106 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
107 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
108 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
109 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
110 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
111 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
112 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/openbmc/qemu/target/arm/
H A Dcpu-sysregs.h.inc2 DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0)
3 DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1)
4 DEF(ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5)
5 DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0)
6 DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1)
7 DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4)
8 DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5)
9 DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0)
10 DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1)
11 DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2)
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8-3a.inc1 DEFAULTTUNE ?= "armv8-3a"
3 TUNEVALID[armv8-3a] = "Enable instructions for ARMv8.3-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', ' -march=armv8.3-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', 'armv8-3a:', '', d)}"
10 AVAILTUNES += "armv8-3a armv8-3a-crypto armv8-3a-crypto-sve"
11 ARMPKGARCH:tune-armv8-3a ?= "armv8-3a"
12 ARMPKGARCH:tune-armv8-3a-crypto ?= "armv8-3a"
13 ARMPKGARCH:tune-armv8-3a-crypto-sve ?= "armv8-3a"
14 TUNE_FEATURES:tune-armv8-3a = "aarch64 armv8-3a"
15 TUNE_FEATURES:tune-armv8-3a-crypto = "${TUNE_FEATURES:tune-armv8-3a} crypto"
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DHotbird-13.0E8 INNER_FEC = 3/4
16 INNER_FEC = 3/4
24 INNER_FEC = 3/4
32 INNER_FEC = 3/4
40 INNER_FEC = 3/4
48 INNER_FEC = 3/4
56 INNER_FEC = 3/4
64 INNER_FEC = 3/4
72 INNER_FEC = 3/4
80 INNER_FEC = 3/4
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H A DNilesat101+102-7.0W8 INNER_FEC = 3/4
16 INNER_FEC = 3/4
24 INNER_FEC = 3/4
32 INNER_FEC = 3/4
40 INNER_FEC = 3/4
48 INNER_FEC = 3/4
56 INNER_FEC = 3/4
64 INNER_FEC = 3/4
72 INNER_FEC = 3/4
80 INNER_FEC = 3/4
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H A DSirius-5.0E9 INNER_FEC = 3/4
17 INNER_FEC = 3/4
25 INNER_FEC = 3/4
33 INNER_FEC = 3/4
41 INNER_FEC = 3/4
49 INNER_FEC = 3/4
57 INNER_FEC = 3/4
73 INNER_FEC = 3/4
81 INNER_FEC = 3/4
89 INNER_FEC = 3/4
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H A DAnik-F3-119W9 INNER_FEC = 2/3
18 INNER_FEC = 2/3
27 INNER_FEC = 2/3
36 INNER_FEC = 2/3
45 INNER_FEC = 2/3
54 INNER_FEC = 2/3
63 INNER_FEC = 2/3
72 INNER_FEC = 2/3
81 INNER_FEC = 2/3
90 INNER_FEC = 2/3
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H A DAmos-4w8 INNER_FEC = 3/4
16 INNER_FEC = 3/4
24 INNER_FEC = 2/3
32 INNER_FEC = 3/4
40 INNER_FEC = 2/3
48 INNER_FEC = 3/4
64 INNER_FEC = 3/4
80 INNER_FEC = 3/4
88 INNER_FEC = 2/3
104 INNER_FEC = 3/4
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H A DAsiaSat3S_C-105.5E1 # AsiaSat 3S 105.5E C-BAND
14 INNER_FEC = 3/4
24 INNER_FEC = 3/4
34 INNER_FEC = 3/4
44 INNER_FEC = 3/4
54 INNER_FEC = 3/4
64 INNER_FEC = 3/4
74 INNER_FEC = 3/4
84 INNER_FEC = 3/4
114 INNER_FEC = 3/4
[all …]
H A DInsat3A_C-93.5E1 # Insat 3A @ 93.5E C-BAND
14 INNER_FEC = 3/4
24 INNER_FEC = 3/4
34 INNER_FEC = 3/4
44 INNER_FEC = 3/4
54 INNER_FEC = 3/4
64 INNER_FEC = 3/4
74 INNER_FEC = 3/4
84 INNER_FEC = 3/4
94 INNER_FEC = 3/4
[all …]
/openbmc/u-boot/examples/standalone/
H A Dppc_setjmp.S12 # define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
26 stw r1,(JB_GPR1*4)(3)
28 stw r2,(JB_GPR2*4)(3)
29 stw r14,((JB_GPRS+0)*4)(3)
30 FP( stfd 14,((JB_FPRS+0*2)*4)(3))
31 stw r0,(JB_LR*4)(3)
32 stw r15,((JB_GPRS+1)*4)(3)
33 FP( stfd 15,((JB_FPRS+1*2)*4)(3))
35 stw r16,((JB_GPRS+2)*4)(3)
36 FP( stfd 16,((JB_FPRS+2*2)*4)(3))
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h22 uint32_t reserved_writeonce[3];
26 uint32_t reserved_entropy[3];
28 uint32_t reserved_entropy_latched[3];
34 uint32_t reserved_hw_digctl_dbgrd[3];
36 uint32_t reserved_hw_digctl_dbg[3];
59 uint32_t reserved_hw_digctl_scratch0[3];
61 uint32_t reserved_hw_digctl_scratch1[3];
63 uint32_t reserved_hw_digctl_armcache[3];
66 uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
68 uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3];
[all …]
H A Diomux-mx28.h23 #define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
45 #define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
78 #define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
101 #define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
102 #define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
103 #define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
104 #define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
105 #define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
106 #define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
107 #define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
78 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
79 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
80 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
81 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
84 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
[all …]
/openbmc/pldm/configurations/events/
H A DstateSensorPdrs.json9 "event_states": [1, 2, 3, 5, 7, 9, 21, 22, 26], number
34 "event_states": [1, 2, 3, 5, 7, 9, 21, 22, 26], number
59 "event_states": [3, 5, 20, 22, 26], number
75 "containerID": 3,
80 "event_states": [1, 3],
90 "containerID": 3,
95 "event_states": [1, 3],
105 "containerID": 3,
110 "event_states": [1, 3],
120 "containerID": 3,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dgrf_rk3128.h101 GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
106 GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
111 GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
134 GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
140 GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
151 GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
157 GPIO0B1_MASK = 3,
163 GPIO0B0_MASK = 3,
191 GPIO0D0_MASK = 3 << GPIO0D0_SHIFT,
200 GPIO1A5_MASK = 3 << GPIO1A5_SHIFT,
[all …]
H A Dgrf_rk3399.h59 u32 reserved11[3];
150 u32 gpio2_sr[3][4];
152 u32 gpio2_smt[3][4];
283 u32 reserved1[3];
328 GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
331 GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
334 GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
339 GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT,
342 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
346 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
[all …]
/openbmc/phosphor-webui/app/assets/icons/
H A Dicon-visibility-on.svg1 …0-3-1.3-3-3s1.3-3 3-3 3 1.3 3 3-1.3 3-3 3z"/><path d="M8 10c2.8 0 5.1-1.5 6.9-4.6C13.1 2.5 10.8 1 …
/openbmc/u-boot/arch/arm/dts/
H A Dsama5d2-pinfunc.h19 #define PIN_PA3 3
89 #define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2)
97 #define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2)
105 #define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2)
113 #define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2)
121 #define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2)
129 #define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2)
142 #define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3)
150 #define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4)
153 #define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3)
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dmsa.decode29 %3r_df_h 21:1 !function=plus_1
30 %3r_df_w 21:1 !function=plus_2
34 @bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
41 @3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
42 @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
43 @3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
97 SLL 011110 000.. ..... ..... ..... 001101 @3r
98 SRA 011110 001.. ..... ..... ..... 001101 @3r
99 SRL 011110 010.. ..... ..... ..... 001101 @3r
100 BCLR 011110 011.. ..... ..... ..... 001101 @3r
[all …]
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dpinmux_config.h1 /* SPDX-License-Identifier: BSD-3-Clause */
24 3, /* EMACIO14 */
25 3, /* EMACIO15 */
26 3, /* EMACIO16 */
27 3, /* EMACIO17 */
28 3, /* EMACIO18 */
29 3, /* EMACIO19 */
30 3, /* FLASHIO0 */
32 3, /* FLASHIO2 */
33 3, /* FLASHIO3 */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1088a_serdes.c17 {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 } },
18 {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
19 {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
20 {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
21 {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
22 {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
23 {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
24 {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
25 {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
27 {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2 }, {4, 4, 3, 1 } },
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dit-All22 CODE_RATE_HP = 2/3
35 CODE_RATE_HP = 2/3
48 CODE_RATE_HP = 2/3
61 CODE_RATE_HP = 2/3
74 CODE_RATE_HP = 2/3
87 CODE_RATE_HP = 2/3
100 CODE_RATE_HP = 2/3
113 CODE_RATE_HP = 2/3
128 CODE_RATE_HP = 2/3
141 CODE_RATE_HP = 2/3
[all …]
H A Dat-All8 CODE_RATE_HP = 3/4
20 CODE_RATE_HP = 3/4
32 CODE_RATE_HP = 3/4
44 CODE_RATE_HP = 3/4
56 CODE_RATE_HP = 3/4
68 CODE_RATE_HP = 3/4
80 CODE_RATE_HP = 3/4
92 CODE_RATE_HP = 3/4
104 CODE_RATE_HP = 3/4
116 CODE_RATE_HP = 3/4
[all …]

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