Lines Matching full:3
59 u32 reserved11[3];
150 u32 gpio2_sr[3][4];
152 u32 gpio2_smt[3][4];
283 u32 reserved1[3];
328 GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
331 GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
334 GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
339 GRF_GPIO2B0_SEL_MASK = 3 << GRF_GPIO2B0_SEL_SHIFT,
342 GRF_GPIO2B1_SEL_MASK = 3 << GRF_GPIO2B1_SEL_SHIFT,
346 GRF_GPIO2B2_SEL_MASK = 3 << GRF_GPIO2B2_SEL_SHIFT,
350 GRF_GPIO2B3_SEL_MASK = 3 << GRF_GPIO2B3_SEL_SHIFT,
353 GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
358 GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
361 GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
364 GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
367 GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
370 GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
373 GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
378 GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
381 GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
384 GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
387 GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
390 GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
394 GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
398 GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
402 GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
408 GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
412 GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
415 GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
418 GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
421 GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
424 GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
429 GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
434 GRF_GPIO4A1_SEL_MASK = 3 << GRF_GPIO4A1_SEL_SHIFT,
437 GRF_GPIO4A2_SEL_MASK = 3 << GRF_GPIO4A2_SEL_SHIFT,
442 GRF_GPIO4B0_SEL_MASK = 3 << GRF_GPIO4B0_SEL_SHIFT,
446 GRF_GPIO4B1_SEL_MASK = 3 << GRF_GPIO4B1_SEL_SHIFT,
450 GRF_GPIO4B2_SEL_MASK = 3 << GRF_GPIO4B2_SEL_SHIFT,
453 GRF_GPIO4B3_SEL_MASK = 3 << GRF_GPIO4B3_SEL_SHIFT,
456 GRF_GPIO4B4_SEL_MASK = 3 << GRF_GPIO4B4_SEL_SHIFT,
459 GRF_GPIO4B5_SEL_MASK = 3 << GRF_GPIO4B5_SEL_SHIFT,
464 GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
466 GRF_HDMII2C_SCL = 3,
468 GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
470 GRF_HDMII2C_SDA = 3,
472 GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
475 GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT,
478 GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT,
481 GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
487 GRF_GPIO3A1_E_SHIFT = 3,
500 GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
509 GRF_GPIO3B1_E_SHIFT = 3,
522 GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
531 GRF_GPIO3C1_E_SHIFT = 3,
544 GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
552 GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
583 PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
588 PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
593 PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
596 PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
599 PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
602 PMUGRF_GPIO1B3_SEL_MASK = 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
605 PMUGRF_GPIO1B4_SEL_MASK = 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
608 PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
611 PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
616 PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
619 PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
622 PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
625 PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
637 RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
639 RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),