Home
last modified time | relevance | path

Searched +full:2 +full:rgmii (Results 1 – 25 of 1011) sorted by relevance

12345678910>>...41

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
15 - compatible : compatible list, contains 2 entries, first is
45 Supported values are: "mii", "rmii", "smii", "rgmii",
47 For Axon on CAB, it is "rgmii"
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
57 For Axon: phandle of plb5/plb4/opb/rgmii
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
143 phy-mode = "rgmii";
[all …]
H A Dxlnx,gmii-to-rgmii.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
24 const: xlnx,gmii-to-rgmii-1.0
51 compatible = "xlnx,gmii-to-rgmii-1.0";
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
33 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
57 drive strength of rx_clk rgmii pad.
58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
74 drive strength of rx_data/rx_ctl rgmii pad.
75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
[all …]
H A Damlogic,meson-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
63 The internal RGMII TX clock delay (provided by this driver) in
64 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
65 When phy-mode is set to "rgmii" then the TX delay should be
66 explicitly configured. When not configured a fallback of 2ns is
67 used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
78 - 2
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
175 phy-mode = "rgmii";
H A Dti,icssg-prueth.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
36 - const: tx0-2
40 - const: tx1-2
57 maxItems: 2
64 maxItems: 2
99 ti,syscon-rgmii-delay:
107 to ICSSG control register for RGMII transmit delay
146 ti,pruss-gp-mux-sel = <2>, /* MII mode */
147 <2>,
148 <2>,
[all …]
H A Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
28 maxItems: 2
33 - const: rgmii
56 - rgmii
85 reg-names = "stmmaceth", "rgmii";
86 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
107 phy-mode = "rgmii";
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
112 1. tx clock will be inversed in MII/RGMII case,
113 2. tx clock inside MAC will be inversed relative to reference clock
122 1. rx clock will be inversed in MII/RGMII case.
123 2. reference clock will be inversed when arrived at MAC in RMII case, when
159 phy-mode = "rgmii-rxid";
H A Dengleder,tsnep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
31 - const: txrx-2
56 - rgmii
57 - rgmii-id
78 #address-cells = <2>;
79 #size-cells = <2>;
86 phy-mode = "rgmii";
103 interrupt-names = "mac", "txrx-1", "txrx-2", "txrx-3";
106 phy-mode = "rgmii";
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
97 should use "rgmii-id" if internal delays are desired as this may be
98 changed in future to cause "rgmii" mode to disable delays.
104 mode 1 or 2. To ensure PHY operation, there are specific actions that
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
38 # Optional container node for the 2 internal MDIO buses of the SJA1110
42 # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
85 - rgmii
86 - rgmii-rxid
87 - rgmii-txid
88 - rgmii-id
154 phy-mode = "rgmii-id";
162 phy-mode = "rgmii-id";
168 port@2 {
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
48 - rgmii
49 - rgmii-id
50 - rgmii-txid
51 - rgmii-rxid
108 port@2 {
109 reg = <2>;
124 phy-mode = "rgmii";
138 phy-mode = "rgmii";
175 t1phy2: ethernet-phy@2{
H A Darrow,xrs700x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 RGMII ports and one RMII port and are managed via i2c or mdio.
54 phy-mode = "rgmii-id";
56 ethernet-port@2 {
57 reg = <2>;
60 phy-mode = "rgmii-id";
65 phy-mode = "rgmii-id";
/openbmc/linux/arch/powerpc/boot/dts/
H A Deiger.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
60 #interrupt-cells = <2>;
70 #interrupt-cells = <2>;
78 cell-index = <2>;
82 #interrupt-cells = <2>;
94 #interrupt-cells = <2>;
111 #address-cells = <2>;
154 #address-cells = <2>;
163 bank-width = <2>;
[all …]
H A Dklondike.dts54 #interrupt-cells = <2>;
64 #interrupt-cells = <2>;
72 cell-index = <2>;
76 #interrupt-cells = <2>;
88 #interrupt-cells = <2>;
108 num-tx-chans = <2>;
131 RGMII0: emac-rgmii@400a2000 {
132 compatible = "ibm,rgmii";
164 phy-mode = "rgmii";
168 rgmii-device = <&RGMII0>;
[all …]
H A Dglacier.dts7 * License version 2. This program is licensed "as is" without
14 #address-cells = <2>;
61 #interrupt-cells = <2>;
71 #interrupt-cells = <2>;
79 cell-index = <2>;
83 #interrupt-cells = <2>;
95 #interrupt-cells = <2>;
122 #address-cells = <2>;
171 #address-cells = <2>;
180 bank-width = <2>;
[all …]
H A Drainier.dts10 * License version 2. This program is licensed "as is" without
18 #address-cells = <2>;
64 #interrupt-cells = <2>;
74 #interrupt-cells = <2>;
82 cell-index = <2>;
86 #interrupt-cells = <2>;
103 #address-cells = <2>;
121 num-tx-chans = <2>;
122 num-rx-chans = <2>;
149 #address-cells = <2>;
[all …]
H A Dobs600.dts11 * License version 2. This program is licensed "as is" without
62 #interrupt-cells = <2>;
72 #interrupt-cells = <2>;
80 cell-index = <2>;
84 #interrupt-cells = <2>;
123 num-tx-chans = <2>;
124 num-rx-chans = <2>;
151 #address-cells = <2>;
160 bank-width = <2>;
238 RGMII0: emac-rgmii@ef600b00 {
[all …]
H A Dfsp2.dts7 * License version 2. This program is licensed "as is" without
15 #address-cells = <2>;
64 #interrupt-cells = <2>;
76 #interrupt-cells = <2>;
90 #interrupt-cells = <2>;
94 cell-index = <2>;
104 #interrupt-cells = <2>;
118 #interrupt-cells = <2>;
131 #interrupt-cells = <2>;
144 #interrupt-cells = <2>;
[all …]
/openbmc/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dmac.c21 u32 intf_ctrl, rgmii; in xge_mac_set_speed() local
26 rgmii = xge_rd_csr(pdata, RGMII_REG_0); in xge_mac_set_speed()
37 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); in xge_mac_set_speed()
44 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); in xge_mac_set_speed()
47 SET_REG_BITS(&mc2, INTF_MODE, 2); in xge_mac_set_speed()
48 SET_REG_BITS(&intf_ctrl, HD_MODE, 2); in xge_mac_set_speed()
49 SET_REG_BITS(&icm0, CFG_MACMODE, 2); in xge_mac_set_speed()
51 SET_REG_BIT(&rgmii, CFG_SPEED_125, 1); in xge_mac_set_speed()
60 xge_wr_csr(pdata, RGMII_REG_0, rgmii); in xge_mac_set_speed()
71 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | in xge_mac_set_station_addr()
/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_hydra.c9 * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
14 * RGMII card.
17 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
45 * 2) An alias for each real and virtual MDIO node that is disabled by default
84 * MDIO bus to a particular RGMII or SGMII PHY.
97 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
216 * 2) An Fman port
255 /* RGMII */ in board_ft_fman_fixup_port()
[all …]
H A Deth_superhydra.c9 * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
12 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
17 * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
45 * 2) An alias for each real and virtual MDIO node that is disabled by default
89 * MDIO bus to a particular RGMII or SGMII PHY.
102 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
199 * 2) An Fman port
220 /* RGMII and XGMII are already mapped correctly in the DTS */ in board_ft_fman_fixup_port()
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-wqe.h10 * it under the terms of the GNU General Public License, Version 2, as
103 * - 2 = L4 Checksum Error: the L4 checksum value is
132 * - 2 = IPv4 Header Checksum Error: the IPv4 header
330 * - 2 = jabber error: the RGMII packet was too large
332 * - 3 = overrun error: the RGMII packet is longer
334 * - 4 = oversize error: the RGMII packet is longer
336 * - 5 = alignment error: the RGMII packet is not an
339 * - 6 = fragment error: the RGMII packet is shorter
341 * - 7 = GMX FCS error: the RGMII packet had an FCS
343 * - 8 = undersize error: the RGMII packet is shorter
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts27 reg_vddio_codec: regulator-2V5 {
29 regulator-name = "2P5V";
62 phy-mode = "rgmii-id";
70 phy-mode = "rgmii-id";
74 port@2 {
78 phy-mode = "rgmii-id";
79 reg = <2>;
86 phy-mode = "rgmii-id";
93 phy-mode = "rgmii";
121 /* RGMII delays added via PCB traces */
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c28 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
36 * cycle of the 125MHz RGMII TX clock):
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
74 * Each step is 200ps. These bits are used with external RGMII PHYs
75 * because RGMII RX only has the small window. cfg_rxclk_dly can
152 { .div = 2, .val = 2, }, in meson8b_init_rgmii_tx_clk()
192 clk_configs->fixed_div2.div = 2; in meson8b_init_rgmii_tx_clk()
220 /* enable RGMII mode */ in meson8b_set_phy_mode()
226 /* disable RGMII mode -> enables RMII mode */ in meson8b_set_phy_mode()
246 /* enable RGMII mode */ in meson_axg_set_phy_mode()
[all …]
/openbmc/u-boot/board/freescale/p2041rdb/
H A Deth.c8 * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs
33 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0
53 lane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2; in initialize_lane_to_slot()
54 lane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2; in initialize_lane_to_slot()
55 lane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2; in initialize_lane_to_slot()
64 * 2) An Fman port
84 /* The RGMII PHY is identified by the MAC connected to it */ in board_ft_fman_fixup_port()
151 * is RGMII, we'll also override its PHY address later. We assume that in board_eth_init()
152 * DTSEC4 and DTSEC5 are used for RGMII. in board_eth_init()
171 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ in board_eth_init()

12345678910>>...41