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/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
H A Dspear1310_clock.c231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
237 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
244 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
245 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/lmbench/lmbench/
H A Dupdate-results-script.patch26 -../bin/$OS/msleep 250
28 +msleep 250
34 -../bin/$OS/msleep 250
36 +msleep 250
42 -../bin/$OS/msleep 250
44 +msleep 250
75 -../bin/$OS/msleep 250
77 +msleep 250
94 echo "Calculating mhz, please wait for a moment..."
95 -MHZ=`../bin/$OS/mhz`
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm632.dtsi44 * SDM632 uses Kryo 250 instead of Cortex A53
65 capacity-dmips-mhz = <1980>;
70 capacity-dmips-mhz = <1980>;
75 capacity-dmips-mhz = <1980>;
80 capacity-dmips-mhz = <1980>;
H A Dmsm8976.dtsi40 capacity-dmips-mhz = <573>;
51 capacity-dmips-mhz = <573>;
62 capacity-dmips-mhz = <573>;
73 capacity-dmips-mhz = <573>;
84 capacity-dmips-mhz = <1024>;
95 capacity-dmips-mhz = <1024>;
106 capacity-dmips-mhz = <1024>;
117 capacity-dmips-mhz = <1024>;
1121 polling-delay-passive = <250>;
1136 polling-delay-passive = <250>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.m54418twr119 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
120 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
121 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
122 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
123 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
124 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz
182 cpufreq = 250 MHz
183 busfreq = 125 MHz
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c20 * XTAL [MHz] 2^(18 - 1)
21 * PLL [MHz] = ------------ * ----------------------
33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
52 { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
57 { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
67 { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
120 /* Test for 40MHz XTAL */ in ar934x_pll_init()
323 printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); in do_ar934x_showclk()
324 printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); in do_ar934x_showclk()
325 printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); in do_ar934x_showclk()
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dbrcm,iproc-clocks.yaml119 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
227 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
339 - const: 250mhz
394 clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
/openbmc/qemu/hw/hppa/
H A Dhppa_hardware.h47 #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
/openbmc/linux/drivers/media/pci/mantis/
H A Dmantis_vp3030.c33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
57 msleep(250); in vp3030_frontend_init()
/openbmc/linux/drivers/clocksource/
H A Dscx200_hrt.c5 * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
25 MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
36 #define HR_TMCLKSEL (1 << 1) /* 1|0 counts at 27|1 MHz */
50 .rating = 250,
80 pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm); in init_hrt_clocksource()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidxu3-common.dtsi58 polling-delay-passive = <250>;
114 * (usually) be: 1800 MHz and 1200 MHz.
129 * further, down to 600 MHz (14 steps for big,
147 polling-delay-passive = <250>;
220 polling-delay-passive = <250>;
293 polling-delay-passive = <250>;
366 polling-delay-passive = <250>;
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
18 "QLA2342", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10a */
20 "QLA2350", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x10c */
21 "QLA2352", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10d */
22 "QLA2352", "Sun 133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x10e */
29 "QLA2360", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x115 */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/
H A Dtypes.h21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
/openbmc/qemu/target/alpha/
H A Dclk_helper.c20 * present it with a well-timed clock fixed at 250MHz. in helper_load_pcc()
/openbmc/u-boot/drivers/video/rockchip/
H A Drk_mipi.c214 {200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23}, in rk_mipi_phy_enable()
233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable()
244 if (ddr_clk / (MHz) <= freq_rang[i][0]) in rk_mipi_phy_enable()
256 * given pixelclock is great than 250M, ddrclk will be fix 1500M. in rk_mipi_phy_enable()
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable()
261 max_prediv = (refclk / (5 * MHz)); in rk_mipi_phy_enable()
262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); in rk_mipi_phy_enable()
/openbmc/linux/drivers/clk/renesas/
H A Dclk-r8a7779.c31 * (MHz) (MHz)
34 * clkzs 250 (1/6) 200 (1/8)
36 * clks 250 (1/6) 200 (1/8)
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_mipi_dsi.c31 #define MHZ(v) ((u32)((v) * 1000000U)) macro
102 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
103 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
104 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
105 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
106 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
107 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
108 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
109 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
110 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
[all …]
/openbmc/linux/drivers/media/tuners/
H A Dmt2131.c99 f_lo1 = (f_lo1 / 250) * 250; in mt2131_set_params()
104 /* Frequency LO1 = 16MHz * (DIV1 + NUM1/8192 ) */ in mt2131_set_params()
109 /* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */ in mt2131_set_params()
229 .frequency_min_hz = 48 * MHz,
230 .frequency_max_hz = 860 * MHz,
/openbmc/u-boot/board/sysam/stmark2/
H A Dsbf_dram_init.S37 * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
38 * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
41 * / \ DDR2 can't be clocked lower than 125Mhz
47 /* cpu / 2 = 125 Mhz for 480 Mhz pll */
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c32 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
33 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
34 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
35 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
36 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
37 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
38 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
43 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
44 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
45 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
106 exit-latency-us = <250>;
128 capacity-dmips-mhz = <1024>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/thermal/
H A Dthermal-zones.yaml266 polling-delay-passive = <250>;
294 /* Corresponds to 1400MHz in OPP table */
301 /* Corresponds to 1000MHz in OPP table */
311 polling-delay-passive = <250>;
333 polling-delay-passive = <250>;
/openbmc/linux/arch/arm/mach-omap2/
H A Domap_hwmod_81xx_data.c101 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
125 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
137 * table 1-73 for devices using 250MHz SYSCLK5 clock.
146 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
153 /* L3 med -> L4 fast peripheral interface running at 250MHz */
181 /* L3 med peripheral interface running at 200MHz */
208 /* L3 med peripheral interface running at 250MHz */

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