| /openbmc/u-boot/lib/zlib/ |
| H A D | trees.h | 1 /* header created automatically with -DGEN_TREES_H */
31 {{237},{ 8}}, {{ 29},{ 8}}, {{157},{ 8}}, {{ 93},{ 8}}, {{221},{ 8}},
57 {{ 72},{ 7}}, {{ 40},{ 7}}, {{104},{ 7}}, {{ 24},{ 7}}, {{ 88},{ 7}},
65 {{ 0},{ 5}}, {{16},{ 5}}, {{ 8},{ 5}}, {{24},{ 5}}, {{ 4},{ 5}},
69 {{ 5},{ 5}}, {{21},{ 5}}, {{13},{ 5}}, {{29},{ 5}}, {{ 3},{ 5}},
88 23, 23, 23, 23, 23, 23, 23, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24,
89 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25,
96 28, 28, 28, 28, 28, 28, 28, 28, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
97 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
98 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, 29,
[all …]
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| /openbmc/linux/arch/powerpc/crypto/ |
| H A D | aes-gcm-p10.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
110 # v15 - v22 - input states
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| H A D | poly1305-p10le_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
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| H A D | chacha-p10le-8x.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
93 SAVE_GPR 24, 192, 1
98 SAVE_GPR 29, 232, 1
107 SAVE_VRS 24, 64, 9
112 SAVE_VRS 29, 144, 9
126 SAVE_VSX 24, 352, 9
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| /openbmc/linux/drivers/gpu/drm/i915/gt/ |
| H A D | intel_gpu_commands.h | 1 /* SPDX-License-Identifier: MIT*/
3 * Copyright © 2003-2018 Intel Corporation
21 #define INSTR_CLIENT_SHIFT 29
30 #define INSTR_26_TO_24_SHIFT 24
150 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
152 * - One can actually load arbitrary many arbitrary registers: Simply issue x
155 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
199 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
203 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_backlight_regs.h | 1 /* SPDX-License-Identifier: MIT */
27 #define BLM_PIPE_SELECT (1 << 29)
28 #define BLM_PIPE_SELECT_IVB (3 << 29)
29 #define BLM_PIPE_A (0 << 29)
30 #define BLM_PIPE_B (1 << 29)
31 #define BLM_PIPE_C (2 << 29) /* ivb + */
35 #define BLM_TRANSCODER_EDP (3 << 29)
36 #define BLM_PIPE(pipe) ((pipe) << 29)
40 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
72 /* New registers for PCH-split platforms. Safe where new bits show up, the
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| /openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
| H A D | regs-clkctrl-mx28.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
15 #include <asm/mach-imx/regs-common.h>
21 uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
24 uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */
62 #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
63 #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
64 #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
65 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
66 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
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| H A D | regs-clkctrl-mx23.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
15 #include <asm/mach-imx/regs-common.h>
21 uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
52 #define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
53 #define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
54 #define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
55 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
56 #define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
57 #define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
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| /openbmc/linux/Documentation/translations/zh_CN/core-api/ |
| H A D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/ |
| H A D | mt76_connac2_mac.h | 1 /* SPDX-License-Identifier: ISC */
46 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
52 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
64 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
80 #define MT_TXD3_SW_POWER_MGMT BIT(29)
104 #define MT_TXD6_TX_RATE GENMASK(29, 16)
115 #define MT_TXD7_UDP_TCP_SUM BIT(29)
133 /* VHT/HE only use bits 0-3 */
137 #define MT_TXS0_BW GENMASK(30, 29)
140 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
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| H A D | mt76_connac3_mac.h | 1 /* SPDX-License-Identifier: ISC */
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
47 #define MT_RXD1_NORMAL_CLM BIT(24)
51 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
64 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
69 #define MT_RXD2_NORMAL_NDATA BIT(29)
82 #define MT_RXD3_NORMAL_FCS_ERR BIT(24)
91 #define MT_RXV_HDR_BAND_IDX BIT(24)
101 /* P-RXV */
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
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| /openbmc/linux/include/linux/netfilter/ |
| H A D | nf_conntrack_h323_types.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
140 eH2250LogicalChannelParameters_mediaChannel = (1 << 29),
148 eH2250LogicalChannelParameters_destination = (1 << 24),
181 = (1 << 29),
206 = (1 << 29),
227 eNetworkAccessParameters_t120SetupProcedure = (1 << 29),
237 eOpenLogicalChannel_encryptionSync = (1 << 29),
255 eSetup_UUIE_destinationAddress = (1 << 29),
260 eSetup_UUIE_sourceCallSignalAddress = (1 << 24),
301 eCallProceeding_UUIE_h245SecurityMode = (1 << 29),
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| /openbmc/linux/drivers/media/pci/zoran/ |
| H A D | zr36057.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
53 #define ZR36057_VDCR_MIN_PIX 24
54 #define ZR36057_VDCR_TRITON BIT(24)
67 #define ZR36057_SPGPPCR_SOFT_RESET BIT(24)
75 #define ZR36057_MCTCR_C_EMPTY BIT(29)
84 #define ZR36057_ISR_GIRQ0 BIT(29)
90 #define ZR36057_ICR_GIRQ0 BIT(29)
93 #define ZR36057_ICR_INT_PIN_EN BIT(24)
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/ |
| H A D | mac.h | 1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
81 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
97 #define MT_RXV2_NSTS GENMASK(29, 27)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/ |
| H A D | mac.h | 1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
73 #define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
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| /openbmc/linux/drivers/gpu/drm/exynos/ |
| H A D | regs-scaler.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
138 #define SCALER_CFG_FILL_EN (1 << 24)
149 #define SCALER_INT_EN_ILLEGAL_BLEND (1 << 24)
177 #define SCALER_INT_STATUS_ILLEGAL_BLEND (1 << 24)
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
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| H A D | regs-fimc.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
52 /* Pre-scaler control 1 */
54 /* Pre-scaler control 2 */
158 /* Y 24th frame start address for output DMA */
168 /* Y 29th frame start address for output DMA */
215 /* CB 24th frame start address for output DMA */
225 /* CB 29th frame start address for output DMA */
272 /* CR 24th frame start address for output DMA */
282 /* CR 29th frame start address for output DMA */
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| /openbmc/linux/Documentation/core-api/ |
| H A D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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| /openbmc/linux/sound/soc/mediatek/mt8186/ |
| H A D | mt8186-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
29 #define AHB_IDLE_EN_EXT_SFT 29
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
39 #define PDN_ADC_SFT 24
40 #define PDN_ADC_MASK_SFT BIT(24)
65 #define PDN_3RD_DAC_PREDIS_SFT 29
66 #define PDN_3RD_DAC_PREDIS_MASK_SFT BIT(29)
105 #define CG_DISABLE_SFT 29
106 #define CG_DISABLE_MASK_SFT BIT(29)
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | w83795.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
18 Addresses scanned: I2C 0x2c - 0x2f
23 - Wei Song (Nuvoton)
24 - Jean Delvare <jdelvare@suse.de>
28 -----------
35 - W83795G
52 24 3VDD 1Ch in12
60 11/ 12 VDSEN17/TR4/TD4 24h in20/temp4
83 29/ 30 PECI/TSI (DTS1) 26h temp7
84 29/ 30 PECI/TSI (DTS2) 27h temp8
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| /openbmc/linux/arch/arm64/crypto/ |
| H A D | sha512-ce-core.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
37 * The SHA-512 round constants
111 ld1 {v8.2d-v11.2d}, [x0]
115 ld1 {v20.2d-v23.2d}, [x3], #64
118 0: ld1 {v12.2d-v15.2d}, [x1], #64
119 ld1 {v16.2d-v19.2d}, [x1], #64
138 // v0 ab cd -- ef gh ab
139 // v1 cd -- ef gh ab cd
140 // v2 ef gh ab cd -- ef
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | tegra_nand.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
10 #define CMD_ALE (1 << 29)
15 #define CMD_AFT_DAT_MASK (1 << 24)
17 #define CMD_AFT_DAT_ENABLE (1 << 24)
67 #define CFG_HW_ECC_CORRECTION_MASK (1 << 29)
69 #define CFG_HW_ECC_CORRECTION_ENABLE (1 << 29)
76 #define CFG_TVALUE_MASK (3 << 24)
78 CFG_TVAL4 = 0 << 24,
79 CFG_TVAL6 = 1 << 24,
80 CFG_TVAL8 = 2 << 24
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| /openbmc/linux/security/apparmor/include/ |
| H A D | sig_names.h | 18 [SIGTRAP] = 5, /* -, 5, - */
19 [SIGABRT] = 6, /* SIGIOT: -, 6, - */
30 [SIGSTKFLT] = 16, /* -, 16, - */
32 [SIGCHLD] = 17, /* 20, 17, 18. SIGCHLD -, -, 18 */
35 [SIGTSTP] = 20, /* 18, 20, 24 */
39 [SIGXCPU] = 24, /* 24, 24, 30 */
42 [SIGPROF] = 27, /* 27, 27, 29 */
44 [SIGIO] = 29, /* SIGPOLL: 23, 29, 22 */
45 [SIGPWR] = 30, /* 29, 30, 19. SIGINFO 29, -, - */
50 [SIGEMT] = 32, /* 7, - , 7 */
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| /openbmc/linux/drivers/media/platform/samsung/exynos4-is/ |
| H A D | fimc-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
38 #define FIMC_REG_CIGCTRL_SELCAM_ITU_A BIT(29)
47 #define FIMC_REG_CIGCTRL_INVPOLHREF BIT(24)
54 /* 0 - selects Writeback A (LCD), 1 - selects Writeback B (LCD/ISP) */
59 /* 0 - ITU601; 1 - ITU709 */
79 #define FIMC_REG_CITRGFMT_YCBCR420 (0 << 29)
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| /openbmc/linux/drivers/usb/dwc2/ |
| H A D | hw.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
67 #define GUSBCFG_FORCEHOSTMODE BIT(29)
72 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
100 #define GRSTCTL_CSFTRST_DONE BIT(29)
116 #define GINTSTS_DISCONNINT BIT(29)
121 #define GINTSTS_PRTINT BIT(24)
180 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
181 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
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