1c8846e10SFelix Fietkau /* SPDX-License-Identifier: ISC */ 2c8846e10SFelix Fietkau 3c8846e10SFelix Fietkau #ifndef __MT7603_MAC_H 4c8846e10SFelix Fietkau #define __MT7603_MAC_H 5c8846e10SFelix Fietkau 6c8846e10SFelix Fietkau #define MT_RXD0_LENGTH GENMASK(15, 0) 7c8846e10SFelix Fietkau #define MT_RXD0_PKT_TYPE GENMASK(31, 29) 8c8846e10SFelix Fietkau 9c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16) 10c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_IP_SUM BIT(23) 11c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24) 12c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_GROUP_1 BIT(25) 13c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_GROUP_2 BIT(26) 14c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_GROUP_3 BIT(27) 15c8846e10SFelix Fietkau #define MT_RXD0_NORMAL_GROUP_4 BIT(28) 16c8846e10SFelix Fietkau 17c8846e10SFelix Fietkau enum rx_pkt_type { 18c8846e10SFelix Fietkau PKT_TYPE_TXS = 0, 19c8846e10SFelix Fietkau PKT_TYPE_TXRXV = 1, 20c8846e10SFelix Fietkau PKT_TYPE_NORMAL = 2, 21c8846e10SFelix Fietkau PKT_TYPE_RX_DUP_RFB = 3, 22c8846e10SFelix Fietkau PKT_TYPE_RX_TMR = 4, 23c8846e10SFelix Fietkau PKT_TYPE_RETRIEVE = 5, 24c8846e10SFelix Fietkau PKT_TYPE_RX_EVENT = 7, 25c8846e10SFelix Fietkau }; 26c8846e10SFelix Fietkau 27c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26) 28c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24) 29c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_HDR_TRANS BIT(23) 30c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22) 31c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16) 32c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8) 33c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6) 34c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_BEACON_UC BIT(5) 35c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_BEACON_MC BIT(4) 36c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_BCAST BIT(3) 37c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_MCAST BIT(2) 38c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_U2M BIT(1) 39c8846e10SFelix Fietkau #define MT_RXD1_NORMAL_HTC_VLD BIT(0) 40c8846e10SFelix Fietkau 41c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_NON_AMPDU BIT(31) 42c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30) 43c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_NDATA BIT(29) 44c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_NULL_FRAME BIT(28) 45c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_FRAG BIT(27) 46c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_UDF_VALID BIT(26) 47c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_LLC_MIS BIT(25) 48c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24) 49c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23) 50c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22) 51c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21) 52c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_ICV_ERR BIT(20) 53c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_CLM BIT(19) 54c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_CM BIT(18) 55c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_FCS_ERR BIT(17) 56c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_SW_BIT BIT(16) 57c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12) 58c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_TID GENMASK(11, 8) 59c8846e10SFelix Fietkau #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0) 60c8846e10SFelix Fietkau 61c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30) 62c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_PF_MODE BIT(29) 63c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19) 64c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_WOL GENMASK(18, 14) 65c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13) 66c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_OFLD GENMASK(12, 11) 67c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_CLS BIT(10) 68c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9) 69c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8) 70c8846e10SFelix Fietkau #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0) 71c8846e10SFelix Fietkau 72c8846e10SFelix Fietkau #define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30) 73c8846e10SFelix Fietkau #define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22) 74c8846e10SFelix Fietkau #define MT_RXV1_HT_NO_SOUND BIT(21) 75c8846e10SFelix Fietkau #define MT_RXV1_HT_SMOOTH BIT(20) 76c8846e10SFelix Fietkau #define MT_RXV1_HT_SHORT_GI BIT(19) 77c8846e10SFelix Fietkau #define MT_RXV1_HT_AGGR BIT(18) 78c8846e10SFelix Fietkau #define MT_RXV1_VHTA1_B22 BIT(17) 79c8846e10SFelix Fietkau #define MT_RXV1_FRAME_MODE GENMASK(16, 15) 80c8846e10SFelix Fietkau #define MT_RXV1_TX_MODE GENMASK(14, 12) 81c8846e10SFelix Fietkau #define MT_RXV1_HT_EXT_LTF GENMASK(11, 10) 82c8846e10SFelix Fietkau #define MT_RXV1_HT_AD_CODE BIT(9) 83c8846e10SFelix Fietkau #define MT_RXV1_HT_STBC GENMASK(8, 7) 84c8846e10SFelix Fietkau #define MT_RXV1_TX_RATE GENMASK(6, 0) 85c8846e10SFelix Fietkau 86c8846e10SFelix Fietkau #define MT_RXV2_VHTA1_B16_B6 GENMASK(31, 21) 87c8846e10SFelix Fietkau #define MT_RXV2_LENGTH GENMASK(20, 0) 88c8846e10SFelix Fietkau 89c8846e10SFelix Fietkau #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29) 90c8846e10SFelix Fietkau #define MT_RXV3_F_AGC1_EQ_CAL BIT(28) 91c8846e10SFelix Fietkau #define MT_RXV3_RCPI1 GENMASK(27, 20) 92c8846e10SFelix Fietkau #define MT_RXV3_F_AGC0_CAL_GAIN GENMASK(19, 17) 93c8846e10SFelix Fietkau #define MT_RXV3_F_AGC0_EQ_CAL BIT(16) 94c8846e10SFelix Fietkau #define MT_RXV3_RCPI0 GENMASK(15, 8) 95c8846e10SFelix Fietkau #define MT_RXV3_SEL_ANT BIT(7) 96c8846e10SFelix Fietkau #define MT_RXV3_ACI_DET_X BIT(6) 97c8846e10SFelix Fietkau #define MT_RXV3_OFDM_FREQ_TRANS_DETECT BIT(5) 98c8846e10SFelix Fietkau #define MT_RXV3_VHTA1_B21_B17 GENMASK(4, 0) 99c8846e10SFelix Fietkau 100c8846e10SFelix Fietkau #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29) 101c8846e10SFelix Fietkau #define MT_RXV4_F_AGC2_EQ_CAL BIT(28) 102c8846e10SFelix Fietkau #define MT_RXV4_IB_RSSI1 GENMASK(27, 20) 103c8846e10SFelix Fietkau #define MT_RXV4_F_AGC_LPF_GAIN_X GENMASK(19, 16) 104c8846e10SFelix Fietkau #define MT_RXV4_WB_RSSI_X GENMASK(15, 8) 105c8846e10SFelix Fietkau #define MT_RXV4_IB_RSSI0 GENMASK(7, 0) 106c8846e10SFelix Fietkau 107c8846e10SFelix Fietkau #define MT_RXV5_LTF_SNR0 GENMASK(31, 26) 108c8846e10SFelix Fietkau #define MT_RXV5_LTF_PROC_TIME GENMASK(25, 19) 109c8846e10SFelix Fietkau #define MT_RXV5_FOE GENMASK(18, 7) 110c8846e10SFelix Fietkau #define MT_RXV5_C_AGC_SATE GENMASK(6, 4) 111c8846e10SFelix Fietkau #define MT_RXV5_F_AGC_LNA_GAIN_0 GENMASK(3, 2) 112c8846e10SFelix Fietkau #define MT_RXV5_F_AGC_LNA_GAIN_1 GENMASK(1, 0) 113c8846e10SFelix Fietkau 114c8846e10SFelix Fietkau #define MT_RXV6_C_AGC_STATE GENMASK(30, 28) 115c8846e10SFelix Fietkau #define MT_RXV6_NS_TS_FIELD GENMASK(27, 25) 116c8846e10SFelix Fietkau #define MT_RXV6_RX_VALID BIT(24) 117c8846e10SFelix Fietkau #define MT_RXV6_NF2 GENMASK(23, 16) 118c8846e10SFelix Fietkau #define MT_RXV6_NF1 GENMASK(15, 8) 119c8846e10SFelix Fietkau #define MT_RXV6_NF0 GENMASK(7, 0) 120c8846e10SFelix Fietkau 121c8846e10SFelix Fietkau enum mt7603_tx_header_format { 122c8846e10SFelix Fietkau MT_HDR_FORMAT_802_3, 123c8846e10SFelix Fietkau MT_HDR_FORMAT_CMD, 124c8846e10SFelix Fietkau MT_HDR_FORMAT_802_11, 125c8846e10SFelix Fietkau MT_HDR_FORMAT_802_11_EXT, 126c8846e10SFelix Fietkau }; 127c8846e10SFelix Fietkau 128c8846e10SFelix Fietkau #define MT_TXD_SIZE (8 * 4) 129c8846e10SFelix Fietkau 130c8846e10SFelix Fietkau #define MT_TXD0_P_IDX BIT(31) 131c8846e10SFelix Fietkau #define MT_TXD0_Q_IDX GENMASK(30, 27) 132c8846e10SFelix Fietkau #define MT_TXD0_UTXB BIT(26) 133c8846e10SFelix Fietkau #define MT_TXD0_UNXV BIT(25) 134c8846e10SFelix Fietkau #define MT_TXD0_UDP_TCP_SUM BIT(24) 135c8846e10SFelix Fietkau #define MT_TXD0_IP_SUM BIT(23) 136c8846e10SFelix Fietkau #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16) 137c8846e10SFelix Fietkau #define MT_TXD0_TX_BYTES GENMASK(15, 0) 138c8846e10SFelix Fietkau 139c8846e10SFelix Fietkau #define MT_TXD1_OWN_MAC GENMASK(31, 26) 140c8846e10SFelix Fietkau #define MT_TXD1_PROTECTED BIT(23) 141c8846e10SFelix Fietkau #define MT_TXD1_TID GENMASK(22, 20) 142c8846e10SFelix Fietkau #define MT_TXD1_NO_ACK BIT(19) 143c8846e10SFelix Fietkau #define MT_TXD1_HDR_PAD GENMASK(18, 16) 144c8846e10SFelix Fietkau #define MT_TXD1_LONG_FORMAT BIT(15) 145c8846e10SFelix Fietkau #define MT_TXD1_HDR_FORMAT GENMASK(14, 13) 146c8846e10SFelix Fietkau #define MT_TXD1_HDR_INFO GENMASK(12, 8) 147c8846e10SFelix Fietkau #define MT_TXD1_WLAN_IDX GENMASK(7, 0) 148c8846e10SFelix Fietkau 149c8846e10SFelix Fietkau #define MT_TXD2_FIX_RATE BIT(31) 150c8846e10SFelix Fietkau #define MT_TXD2_TIMING_MEASURE BIT(30) 151c8846e10SFelix Fietkau #define MT_TXD2_BA_DISABLE BIT(29) 152c8846e10SFelix Fietkau #define MT_TXD2_POWER_OFFSET GENMASK(28, 24) 153c8846e10SFelix Fietkau #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16) 154c8846e10SFelix Fietkau #define MT_TXD2_FRAG GENMASK(15, 14) 155c8846e10SFelix Fietkau #define MT_TXD2_HTC_VLD BIT(13) 156c8846e10SFelix Fietkau #define MT_TXD2_DURATION BIT(12) 157c8846e10SFelix Fietkau #define MT_TXD2_BIP BIT(11) 158c8846e10SFelix Fietkau #define MT_TXD2_MULTICAST BIT(10) 159c8846e10SFelix Fietkau #define MT_TXD2_RTS BIT(9) 160c8846e10SFelix Fietkau #define MT_TXD2_SOUNDING BIT(8) 161c8846e10SFelix Fietkau #define MT_TXD2_NDPA BIT(7) 162c8846e10SFelix Fietkau #define MT_TXD2_NDP BIT(6) 163c8846e10SFelix Fietkau #define MT_TXD2_FRAME_TYPE GENMASK(5, 4) 164c8846e10SFelix Fietkau #define MT_TXD2_SUB_TYPE GENMASK(3, 0) 165c8846e10SFelix Fietkau 166c8846e10SFelix Fietkau #define MT_TXD3_SN_VALID BIT(31) 167c8846e10SFelix Fietkau #define MT_TXD3_PN_VALID BIT(30) 168c8846e10SFelix Fietkau #define MT_TXD3_SEQ GENMASK(27, 16) 169c8846e10SFelix Fietkau #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11) 170c8846e10SFelix Fietkau #define MT_TXD3_TX_COUNT GENMASK(10, 6) 171c8846e10SFelix Fietkau 172c8846e10SFelix Fietkau #define MT_TXD4_PN_LOW GENMASK(31, 0) 173c8846e10SFelix Fietkau 174c8846e10SFelix Fietkau #define MT_TXD5_PN_HIGH GENMASK(31, 16) 175c8846e10SFelix Fietkau #define MT_TXD5_SW_POWER_MGMT BIT(13) 176c8846e10SFelix Fietkau #define MT_TXD5_BA_SEQ_CTRL BIT(12) 177c8846e10SFelix Fietkau #define MT_TXD5_DA_SELECT BIT(11) 178c8846e10SFelix Fietkau #define MT_TXD5_TX_STATUS_HOST BIT(10) 179c8846e10SFelix Fietkau #define MT_TXD5_TX_STATUS_MCU BIT(9) 180c8846e10SFelix Fietkau #define MT_TXD5_TX_STATUS_FMT BIT(8) 181c8846e10SFelix Fietkau #define MT_TXD5_PID GENMASK(7, 0) 182c8846e10SFelix Fietkau 183c8846e10SFelix Fietkau #define MT_TXD6_SGI BIT(31) 184c8846e10SFelix Fietkau #define MT_TXD6_LDPC BIT(30) 185c8846e10SFelix Fietkau #define MT_TXD6_TX_RATE GENMASK(29, 18) 186c8846e10SFelix Fietkau #define MT_TXD6_I_TXBF BIT(17) 187c8846e10SFelix Fietkau #define MT_TXD6_E_TXBF BIT(16) 188c8846e10SFelix Fietkau #define MT_TXD6_DYN_BW BIT(15) 189c8846e10SFelix Fietkau #define MT_TXD6_ANT_PRI GENMASK(14, 12) 190c8846e10SFelix Fietkau #define MT_TXD6_SPE_EN BIT(11) 191c8846e10SFelix Fietkau #define MT_TXD6_FIXED_BW BIT(10) 192c8846e10SFelix Fietkau #define MT_TXD6_BW GENMASK(9, 8) 193c8846e10SFelix Fietkau #define MT_TXD6_ANT_ID GENMASK(7, 2) 194c8846e10SFelix Fietkau #define MT_TXD6_FIXED_RATE BIT(0) 195c8846e10SFelix Fietkau 196c8846e10SFelix Fietkau #define MT_TX_RATE_STBC BIT(11) 197c8846e10SFelix Fietkau #define MT_TX_RATE_NSS GENMASK(10, 9) 198c8846e10SFelix Fietkau #define MT_TX_RATE_MODE GENMASK(8, 6) 199c8846e10SFelix Fietkau #define MT_TX_RATE_IDX GENMASK(5, 0) 200c8846e10SFelix Fietkau 201c8846e10SFelix Fietkau #define MT_TXS0_ANTENNA GENMASK(31, 26) 202c8846e10SFelix Fietkau #define MT_TXS0_TID GENMASK(25, 22) 203c8846e10SFelix Fietkau #define MT_TXS0_BA_ERROR BIT(22) 204c8846e10SFelix Fietkau #define MT_TXS0_PS_FLAG BIT(21) 205c8846e10SFelix Fietkau #define MT_TXS0_TXOP_TIMEOUT BIT(20) 206c8846e10SFelix Fietkau #define MT_TXS0_BIP_ERROR BIT(19) 207c8846e10SFelix Fietkau 208c8846e10SFelix Fietkau #define MT_TXS0_QUEUE_TIMEOUT BIT(18) 209c8846e10SFelix Fietkau #define MT_TXS0_RTS_TIMEOUT BIT(17) 210c8846e10SFelix Fietkau #define MT_TXS0_ACK_TIMEOUT BIT(16) 211c8846e10SFelix Fietkau #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16) 212c8846e10SFelix Fietkau 213c8846e10SFelix Fietkau #define MT_TXS0_TX_STATUS_HOST BIT(15) 214c8846e10SFelix Fietkau #define MT_TXS0_TX_STATUS_MCU BIT(14) 215c8846e10SFelix Fietkau #define MT_TXS0_TXS_FORMAT BIT(13) 216c8846e10SFelix Fietkau #define MT_TXS0_FIXED_RATE BIT(12) 217c8846e10SFelix Fietkau #define MT_TXS0_TX_RATE GENMASK(11, 0) 218c8846e10SFelix Fietkau 219c8846e10SFelix Fietkau #define MT_TXS1_F0_TIMESTAMP GENMASK(31, 0) 220c8846e10SFelix Fietkau #define MT_TXS1_F1_NOISE_2 GENMASK(23, 16) 221c8846e10SFelix Fietkau #define MT_TXS1_F1_NOISE_1 GENMASK(15, 8) 222c8846e10SFelix Fietkau #define MT_TXS1_F1_NOISE_0 GENMASK(7, 0) 223c8846e10SFelix Fietkau 224c8846e10SFelix Fietkau #define MT_TXS2_F0_FRONT_TIME GENMASK(24, 0) 225c8846e10SFelix Fietkau #define MT_TXS2_F1_RCPI_2 GENMASK(23, 16) 226c8846e10SFelix Fietkau #define MT_TXS2_F1_RCPI_1 GENMASK(15, 8) 227c8846e10SFelix Fietkau #define MT_TXS2_F1_RCPI_0 GENMASK(7, 0) 228c8846e10SFelix Fietkau 229c8846e10SFelix Fietkau #define MT_TXS3_WCID GENMASK(31, 24) 230c8846e10SFelix Fietkau #define MT_TXS3_RXV_SEQNO GENMASK(23, 16) 231c8846e10SFelix Fietkau #define MT_TXS3_TX_DELAY GENMASK(15, 0) 232c8846e10SFelix Fietkau 233c8846e10SFelix Fietkau #define MT_TXS4_LAST_TX_RATE GENMASK(31, 29) 234c8846e10SFelix Fietkau #define MT_TXS4_TX_COUNT GENMASK(28, 24) 235c8846e10SFelix Fietkau #define MT_TXS4_AMPDU BIT(23) 236c8846e10SFelix Fietkau #define MT_TXS4_ACKED_MPDU BIT(22) 237c8846e10SFelix Fietkau #define MT_TXS4_PID GENMASK(21, 14) 238c8846e10SFelix Fietkau #define MT_TXS4_BW GENMASK(13, 12) 239c8846e10SFelix Fietkau #define MT_TXS4_F0_SEQNO GENMASK(11, 0) 240c8846e10SFelix Fietkau #define MT_TXS4_F1_TSSI GENMASK(11, 0) 241c8846e10SFelix Fietkau 242c8846e10SFelix Fietkau #endif 243