xref: /openbmc/linux/drivers/media/pci/zoran/zr36057.h (revision 2a0c2806)
1*2a0c2806SHans Verkuil /* SPDX-License-Identifier: GPL-2.0-or-later */
2*2a0c2806SHans Verkuil /*
3*2a0c2806SHans Verkuil  * zr36057.h - zr36057 register offsets
4*2a0c2806SHans Verkuil  *
5*2a0c2806SHans Verkuil  * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
6*2a0c2806SHans Verkuil  */
7*2a0c2806SHans Verkuil 
8*2a0c2806SHans Verkuil #ifndef _ZR36057_H_
9*2a0c2806SHans Verkuil #define _ZR36057_H_
10*2a0c2806SHans Verkuil 
11*2a0c2806SHans Verkuil /* Zoran ZR36057 registers */
12*2a0c2806SHans Verkuil 
13*2a0c2806SHans Verkuil #define ZR36057_VFEHCR          0x000	/* Video Front End, Horizontal Configuration Register */
14*2a0c2806SHans Verkuil #define ZR36057_VFEHCR_HS_POL           BIT(30)
15*2a0c2806SHans Verkuil #define ZR36057_VFEHCR_H_START          10
16*2a0c2806SHans Verkuil #define ZR36057_VFEHCR_H_END		0
17*2a0c2806SHans Verkuil #define ZR36057_VFEHCR_HMASK		0x3ff
18*2a0c2806SHans Verkuil 
19*2a0c2806SHans Verkuil #define ZR36057_VFEVCR          0x004	/* Video Front End, Vertical Configuration Register */
20*2a0c2806SHans Verkuil #define ZR36057_VFEVCR_VS_POL           BIT(30)
21*2a0c2806SHans Verkuil #define ZR36057_VFEVCR_V_START          10
22*2a0c2806SHans Verkuil #define ZR36057_VFEVCR_V_END		0
23*2a0c2806SHans Verkuil #define ZR36057_VFEVCR_VMASK		0x3ff
24*2a0c2806SHans Verkuil 
25*2a0c2806SHans Verkuil #define ZR36057_VFESPFR         0x008	/* Video Front End, Scaler and Pixel Format Register */
26*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_EXT_FL          BIT(26)
27*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_TOP_FIELD       BIT(25)
28*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_VCLK_POL        BIT(24)
29*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_H_FILTER        21
30*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_HOR_DCM         14
31*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_VER_DCM         8
32*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_DISP_MODE       6
33*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_YUV422          (0 << 3)
34*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_RGB888          (1 << 3)
35*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_RGB565          (2 << 3)
36*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_RGB555          (3 << 3)
37*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_ERR_DIF         BIT(2)
38*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_PACK24          BIT(1)
39*2a0c2806SHans Verkuil #define ZR36057_VFESPFR_LITTLE_ENDIAN   BIT(0)
40*2a0c2806SHans Verkuil 
41*2a0c2806SHans Verkuil #define ZR36057_VDTR            0x00c	/* Video Display "Top" Register */
42*2a0c2806SHans Verkuil 
43*2a0c2806SHans Verkuil #define ZR36057_VDBR            0x010	/* Video Display "Bottom" Register */
44*2a0c2806SHans Verkuil 
45*2a0c2806SHans Verkuil #define ZR36057_VSSFGR          0x014	/* Video Stride, Status, and Frame Grab Register */
46*2a0c2806SHans Verkuil #define ZR36057_VSSFGR_DISP_STRIDE      16
47*2a0c2806SHans Verkuil #define ZR36057_VSSFGR_VID_OVF          BIT(8)
48*2a0c2806SHans Verkuil #define ZR36057_VSSFGR_SNAP_SHOT        BIT(1)
49*2a0c2806SHans Verkuil #define ZR36057_VSSFGR_FRAME_GRAB       BIT(0)
50*2a0c2806SHans Verkuil 
51*2a0c2806SHans Verkuil #define ZR36057_VDCR            0x018	/* Video Display Configuration Register */
52*2a0c2806SHans Verkuil #define ZR36057_VDCR_VID_EN             BIT(31)
53*2a0c2806SHans Verkuil #define ZR36057_VDCR_MIN_PIX            24
54*2a0c2806SHans Verkuil #define ZR36057_VDCR_TRITON             BIT(24)
55*2a0c2806SHans Verkuil #define ZR36057_VDCR_VID_WIN_HT         12
56*2a0c2806SHans Verkuil #define ZR36057_VDCR_VID_WIN_WID        0
57*2a0c2806SHans Verkuil 
58*2a0c2806SHans Verkuil #define ZR36057_MMTR            0x01c	/* Masking Map "Top" Register */
59*2a0c2806SHans Verkuil 
60*2a0c2806SHans Verkuil #define ZR36057_MMBR            0x020	/* Masking Map "Bottom" Register */
61*2a0c2806SHans Verkuil 
62*2a0c2806SHans Verkuil #define ZR36057_OCR             0x024	/* Overlay Control Register */
63*2a0c2806SHans Verkuil #define ZR36057_OCR_OVL_ENABLE          BIT(15)
64*2a0c2806SHans Verkuil #define ZR36057_OCR_MASK_STRIDE         0
65*2a0c2806SHans Verkuil 
66*2a0c2806SHans Verkuil #define ZR36057_SPGPPCR         0x028	/* System, PCI, and General Purpose Pins Control Register */
67*2a0c2806SHans Verkuil #define ZR36057_SPGPPCR_SOFT_RESET	BIT(24)
68*2a0c2806SHans Verkuil 
69*2a0c2806SHans Verkuil #define ZR36057_GPPGCR1         0x02c	/* General Purpose Pins and GuestBus Control Register (1) */
70*2a0c2806SHans Verkuil 
71*2a0c2806SHans Verkuil #define ZR36057_MCSAR           0x030	/* MPEG Code Source Address Register */
72*2a0c2806SHans Verkuil 
73*2a0c2806SHans Verkuil #define ZR36057_MCTCR           0x034	/* MPEG Code Transfer Control Register */
74*2a0c2806SHans Verkuil #define ZR36057_MCTCR_COD_TIME          BIT(30)
75*2a0c2806SHans Verkuil #define ZR36057_MCTCR_C_EMPTY           BIT(29)
76*2a0c2806SHans Verkuil #define ZR36057_MCTCR_C_FLUSH           BIT(28)
77*2a0c2806SHans Verkuil #define ZR36057_MCTCR_COD_GUEST_ID	20
78*2a0c2806SHans Verkuil #define ZR36057_MCTCR_COD_GUEST_REG	16
79*2a0c2806SHans Verkuil 
80*2a0c2806SHans Verkuil #define ZR36057_MCMPR           0x038	/* MPEG Code Memory Pointer Register */
81*2a0c2806SHans Verkuil 
82*2a0c2806SHans Verkuil #define ZR36057_ISR             0x03c	/* Interrupt Status Register */
83*2a0c2806SHans Verkuil #define ZR36057_ISR_GIRQ1               BIT(30)
84*2a0c2806SHans Verkuil #define ZR36057_ISR_GIRQ0               BIT(29)
85*2a0c2806SHans Verkuil #define ZR36057_ISR_COD_REP_IRQ         BIT(28)
86*2a0c2806SHans Verkuil #define ZR36057_ISR_JPEG_REP_IRQ        BIT(27)
87*2a0c2806SHans Verkuil 
88*2a0c2806SHans Verkuil #define ZR36057_ICR             0x040	/* Interrupt Control Register */
89*2a0c2806SHans Verkuil #define ZR36057_ICR_GIRQ1               BIT(30)
90*2a0c2806SHans Verkuil #define ZR36057_ICR_GIRQ0               BIT(29)
91*2a0c2806SHans Verkuil #define ZR36057_ICR_COD_REP_IRQ         BIT(28)
92*2a0c2806SHans Verkuil #define ZR36057_ICR_JPEG_REP_IRQ        BIT(27)
93*2a0c2806SHans Verkuil #define ZR36057_ICR_INT_PIN_EN          BIT(24)
94*2a0c2806SHans Verkuil 
95*2a0c2806SHans Verkuil #define ZR36057_I2CBR           0x044	/* I2C Bus Register */
96*2a0c2806SHans Verkuil #define ZR36057_I2CBR_SDA		BIT(1)
97*2a0c2806SHans Verkuil #define ZR36057_I2CBR_SCL		BIT(0)
98*2a0c2806SHans Verkuil 
99*2a0c2806SHans Verkuil #define ZR36057_JMC             0x100	/* JPEG Mode and Control */
100*2a0c2806SHans Verkuil #define ZR36057_JMC_JPG                 BIT(31)
101*2a0c2806SHans Verkuil #define ZR36057_JMC_JPG_EXP_MODE        (0 << 29)
102*2a0c2806SHans Verkuil #define ZR36057_JMC_JPG_CMP_MODE        BIT(29)
103*2a0c2806SHans Verkuil #define ZR36057_JMC_MJPG_EXP_MODE       (2 << 29)
104*2a0c2806SHans Verkuil #define ZR36057_JMC_MJPG_CMP_MODE       (3 << 29)
105*2a0c2806SHans Verkuil #define ZR36057_JMC_RTBUSY_FB           BIT(6)
106*2a0c2806SHans Verkuil #define ZR36057_JMC_GO_EN               BIT(5)
107*2a0c2806SHans Verkuil #define ZR36057_JMC_SYNC_MSTR           BIT(4)
108*2a0c2806SHans Verkuil #define ZR36057_JMC_FLD_PER_BUFF        BIT(3)
109*2a0c2806SHans Verkuil #define ZR36057_JMC_VFIFO_FB            BIT(2)
110*2a0c2806SHans Verkuil #define ZR36057_JMC_CFIFO_FB            BIT(1)
111*2a0c2806SHans Verkuil #define ZR36057_JMC_STLL_LIT_ENDIAN     BIT(0)
112*2a0c2806SHans Verkuil 
113*2a0c2806SHans Verkuil #define ZR36057_JPC             0x104	/* JPEG Process Control */
114*2a0c2806SHans Verkuil #define ZR36057_JPC_P_RESET             BIT(7)
115*2a0c2806SHans Verkuil #define ZR36057_JPC_COD_TRNS_EN         BIT(5)
116*2a0c2806SHans Verkuil #define ZR36057_JPC_ACTIVE              BIT(0)
117*2a0c2806SHans Verkuil 
118*2a0c2806SHans Verkuil #define ZR36057_VSP             0x108	/* Vertical Sync Parameters */
119*2a0c2806SHans Verkuil #define ZR36057_VSP_VSYNC_SIZE          16
120*2a0c2806SHans Verkuil #define ZR36057_VSP_FRM_TOT             0
121*2a0c2806SHans Verkuil 
122*2a0c2806SHans Verkuil #define ZR36057_HSP             0x10c	/* Horizontal Sync Parameters */
123*2a0c2806SHans Verkuil #define ZR36057_HSP_HSYNC_START         16
124*2a0c2806SHans Verkuil #define ZR36057_HSP_LINE_TOT            0
125*2a0c2806SHans Verkuil 
126*2a0c2806SHans Verkuil #define ZR36057_FHAP            0x110	/* Field Horizontal Active Portion */
127*2a0c2806SHans Verkuil #define ZR36057_FHAP_NAX                16
128*2a0c2806SHans Verkuil #define ZR36057_FHAP_PAX                0
129*2a0c2806SHans Verkuil 
130*2a0c2806SHans Verkuil #define ZR36057_FVAP            0x114	/* Field Vertical Active Portion */
131*2a0c2806SHans Verkuil #define ZR36057_FVAP_NAY                16
132*2a0c2806SHans Verkuil #define ZR36057_FVAP_PAY                0
133*2a0c2806SHans Verkuil 
134*2a0c2806SHans Verkuil #define ZR36057_FPP             0x118	/* Field Process Parameters */
135*2a0c2806SHans Verkuil #define ZR36057_FPP_ODD_EVEN            BIT(0)
136*2a0c2806SHans Verkuil 
137*2a0c2806SHans Verkuil #define ZR36057_JCBA            0x11c	/* JPEG Code Base Address */
138*2a0c2806SHans Verkuil 
139*2a0c2806SHans Verkuil #define ZR36057_JCFT            0x120	/* JPEG Code FIFO Threshold */
140*2a0c2806SHans Verkuil 
141*2a0c2806SHans Verkuil #define ZR36057_JCGI            0x124	/* JPEG Codec Guest ID */
142*2a0c2806SHans Verkuil #define ZR36057_JCGI_JPE_GUEST_ID       4
143*2a0c2806SHans Verkuil #define ZR36057_JCGI_JPE_GUEST_REG      0
144*2a0c2806SHans Verkuil 
145*2a0c2806SHans Verkuil #define ZR36057_GCR2            0x12c	/* GuestBus Control Register (2) */
146*2a0c2806SHans Verkuil 
147*2a0c2806SHans Verkuil #define ZR36057_POR             0x200	/* Post Office Register */
148*2a0c2806SHans Verkuil #define ZR36057_POR_PO_PEN              BIT(25)
149*2a0c2806SHans Verkuil #define ZR36057_POR_PO_TIME             BIT(24)
150*2a0c2806SHans Verkuil #define ZR36057_POR_PO_DIR              BIT(23)
151*2a0c2806SHans Verkuil 
152*2a0c2806SHans Verkuil #define ZR36057_STR             0x300	/* "Still" Transfer Register */
153*2a0c2806SHans Verkuil 
154*2a0c2806SHans Verkuil #endif
155