Home
last modified time | relevance | path

Searched +full:1 +full:c000 (Results 1 – 25 of 376) sorted by relevance

12345678910>>...16

/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
35 #interrupt-cells = <1>;
40 cpu1: cpu@1 {
45 d-tlb-sets = <1>;
51 i-tlb-sets = <1>;
54 reg = <1>;
59 #interrupt-cells = <1>;
69 d-tlb-sets = <1>;
75 i-tlb-sets = <1>;
[all …]
H A Dfu740-c000.dtsi11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
36 #interrupt-cells = <1>;
41 cpu1: cpu@1 {
46 d-tlb-sets = <1>;
52 i-tlb-sets = <1>;
60 #interrupt-cells = <1>;
70 d-tlb-sets = <1>;
76 i-tlb-sets = <1>;
84 #interrupt-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
37 - sifive,fu540-c000-ccache
38 - sifive,fu740-c000-ccache
46 - const: sifive,fu540-c000-ccache
72 maxItems: 1
77 maxItems: 1
90 - sifive,fu740-c000-ccache
113 - sifive,fu740-c000-ccache
157 compatible = "sifive,fu540-c000-ccache", "cache";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 - sifive,fu540-c000-pdma
37 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
42 maxItems: 1
45 minItems: 1
50 minimum: 1
55 const: 1
67 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
35 compatible strings are "sifive,fu540-c000-pwm" and
36 "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
42 maxItems: 1
45 maxItems: 1
53 Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
66 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
22 maxItems: 1
27 minItems: 1
36 maxItems: 1
45 minimum: 1
50 minItems: 1
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
81 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
37 minItems: 1
43 maxItems: 1
46 maxItems: 1
62 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
76 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
81 #address-cells = <1>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-pmics.dtsi14 #address-cells = <1>;
25 pmm8540a_gpios: gpio@c000 {
39 #address-cells = <1>;
45 #address-cells = <1>;
46 #size-cells = <1>;
51 pmm8540c_gpios: gpio@c000 {
65 #address-cells = <1>;
68 pmm8540e_gpios: gpio@c000 {
82 #address-cells = <1>;
85 pmm8540g_gpios: gpio@c000 {
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dopencores,i2c-ocores.yaml21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
22 - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
29 maxItems: 1
32 maxItems: 1
35 maxItems: 1
55 enum: [1, 2, 4]
93 #address-cells = <1>;
99 reg-io-width = <1>; /* 8 bit read/write */
105 #address-cells = <1>;
112 reg-io-width = <1>; /* 8 bit read/write */
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
38 maxItems: 1
41 maxItems: 1
44 maxItems: 1
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
/openbmc/openbmc/meta-quanta/meta-gbs/recipes-phosphor/sensors/
H A Dphosphor-hwmon_%.bbappend8 i2c@85000/i2c-switch@71/i2c@1/max31725@55 \
12 i2c@89000/i2c-switch@71/i2c@1/vrm@61 \
15 i2c@8c000/max34451@4e \
16 i2c@8c000/vrm@5d \
17 i2c@8c000/vrm@5e \
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi52 #size-cells = <1>;
66 #interrupt-cells = <1>;
75 0000 0 0 1 &mpic 40 1 0 0
76 0000 0 0 2 &mpic 1 1 0 0
77 0000 0 0 3 &mpic 2 1 0 0
78 0000 0 0 4 &mpic 3 1 0 0
92 #interrupt-cells = <1>;
101 0000 0 0 1 &mpic 41 1 0 0
102 0000 0 0 2 &mpic 5 1 0 0
103 0000 0 0 3 &mpic 6 1 0 0
[all …]
H A Db4860si-post.dtsi44 interrupts = <16 2 1 20>;
53 cell-index = <1>;
116 bman-portal@3c000 {
136 bman-portal@4c000 {
156 bman-portal@5c000 {
175 qportal15: qman-portal@3c000 {
199 qportal19: qman-portal@4c000 {
223 qportal23: qman-portal@5c000 {
241 interrupts = <16 2 1 9>;
261 /include/ "qoriq-fman3-0-1g-4.dtsi"
[all …]
H A Db4si-post.dtsi52 #size-cells = <1>;
67 #interrupt-cells = <1>;
76 0000 0 0 1 &mpic 40 1 0 0
77 0000 0 0 2 &mpic 1 1 0 0
78 0000 0 0 3 &mpic 2 1 0 0
79 0000 0 0 4 &mpic 3 1 0 0
85 #address-cells = <1>;
86 #size-cells = <1>;
166 bman-portal@c000 {
186 bman-portal@1c000 {
[all …]
H A Dt2081si-post.dtsi52 #size-cells = <1>;
68 #interrupt-cells = <1>;
76 0000 0 0 1 &mpic 40 1 0 0
77 0000 0 0 2 &mpic 1 1 0 0
78 0000 0 0 3 &mpic 2 1 0 0
79 0000 0 0 4 &mpic 3 1 0 0
95 #interrupt-cells = <1>;
103 0000 0 0 1 &mpic 41 1 0 0
104 0000 0 0 2 &mpic 5 1 0 0
105 0000 0 0 3 &mpic 6 1 0 0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi13 #address-cells = <1>;
14 #size-cells = <1>;
19 #address-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
57 #address-cells = <1>;
58 #size-cells = <1>;
89 #address-cells = <1>;
90 #size-cells = <1>;
124 #address-cells = <1>;
[all …]
/openbmc/qemu/include/hw/misc/
H A Dsifive_u_prci.h35 * Current FU540-C000 manual says ready bit is at bit 29, but
36 * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
39 * see https://github.com/sifive/freedom-u540-c000-bootloader
42 #define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
43 #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
46 #define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
49 #define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
50 #define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
53 #define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
56 #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
63 minItems: 1
66 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
69 minItems: 1
74 minItems: 1
78 minItems: 1
93 maxItems: 1
96 maxItems: 1
102 maxItems: 1
107 maxItems: 1
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi8 #address-cells = <1>;
9 #size-cells = <1>;
31 #address-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <1>;
58 #interrupt-cells = <1>;
67 #dma-cells = <1>;
77 nand-controller@8000c000 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml26 const: sifive,fu540-c000-prci
29 maxItems: 1
42 const: 1
55 compatible = "sifive,fu540-c000-prci";
58 #clock-cells = <1>;
H A Dfu740-prci.yaml27 const: sifive,fu740-c000-prci
30 maxItems: 1
43 const: 1
46 const: 1
59 compatible = "sifive,fu740-c000-prci";
62 #clock-cells = <1>;
63 #reset-cells = <1>;
/openbmc/u-boot/arch/arm/dts/
H A Drk3xxx.dtsi34 #address-cells = <1>;
35 #size-cells = <1>;
42 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
43 #dma-cells = <1>;
49 dmac1_ns: dma-controller@2001c000 {
53 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
54 #dma-cells = <1>;
66 #dma-cells = <1>;
87 scu@1013c000 {
119 reg-io-width = <1>;
[all …]
H A Dtegra30-tamonten.dtsi16 i2c0 = "/i2c@7000c000";
28 i2c@7000c000 {
76 #address-cells = <1>;
H A Dtegra210-p2571.dts15 i2c1 = "/i2c@7000c000";
32 i2c@7000c000 {
79 cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
97 #address-cells = <1>;
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml33 - sifive,fu540-c000-clint # SiFive FU540
54 maxItems: 1
57 minItems: 1
70 compatible = "sifive,fu540-c000-clint", "sifive,clint0";

12345678910>>...16