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/openbmc/linux/include/linux/usb/
H A Dpd.h30 PD_CTRL_NOT_SUPP = 16,
51 /* 16-31 Reserved */
231 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
234 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
237 #define PDO_FIXED(mv, ma, flags) \ argument
239 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
241 #define VSAFE5V 5000 /* mv units */
243 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
244 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
247 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h34 #define NUM_GFXCLK_DPM_LEVELS 16
94 #define FEATURE_DS_DCEFCLK_BIT 16
211 #define THROTTLER_PPT3_BIT 16
267 #define RLC_PACE_TABLE_NUM_LEVELS 16
268 #define SIENNA_CICHLID_UMC_CHANNEL_NUM 16
295 #define NUM_I2C_CONTROLLERS 16
528 XGMI_LINK_RATE_16 = 16, // 16Gbps
633 uint16_t SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS]; // mV(Q2)
636 uint16_t PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //In mV(Q2)
646 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
[all …]
H A Dsmu13_driver_if_aldebaran.h54 #define FEATURE_PPT_BIT 16
127 #define THORTTLER_SPARE_16 16
292 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
293 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
342 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
347 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
348 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
349 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
[all …]
H A Dsmu11_driver_if_arcturus.h34 #define NUM_GFXCLK_DPM_LEVELS 16
74 #define FEATURE_PPT_BIT 16
203 #define THROTTLER_VRHOT0_BIT 16
433 XGMI_LINK_RATE_16 = 16, // 16Gbps
452 XGMI_LINK_WIDTH_16 = 16, // x16
497 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
504 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
505 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
506 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
507 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
[all …]
H A Dsmu11_driver_if_navi10.h35 #define NUM_GFXCLK_DPM_LEVELS 16
89 #define FEATURE_FW_DSTATE_BIT 16
190 #define THROTTLER_PPT2_BIT 16
558 uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
559 uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
569 uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
570 uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
574 uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
575 uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
576 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
[all …]
H A Dsmu13_driver_if_v13_0_0.h32 #define NUM_GFXCLK_DPM_LEVELS 16
64 #define FEATURE_DS_UCLK_BIT 16
202 #define THROTTLER_PPT0_BIT 16
227 #define FW_DSTATE_UCP_DS_BIT 16
263 DRAM_BIT_WIDTH_X_16 = 16,
863 uint16_t InitGfx; // In mV(Q2) , should be 0?
864 uint16_t InitSoc; // In mV(Q2)
865 uint16_t InitU; // In Mv(Q2)
919 uint16_t DcTol; // mV Q2
920 uint16_t DcBtcGb; // mV Q2
[all …]
H A Dsmu13_driver_if_v13_0_7.h33 #define NUM_GFXCLK_DPM_LEVELS 16
65 #define FEATURE_DS_UCLK_BIT 16
203 #define THROTTLER_PPT0_BIT 16
228 #define FW_DSTATE_UCP_DS_BIT 16
264 DRAM_BIT_WIDTH_X_16 = 16,
872 uint16_t InitGfx; // In mV(Q2) , should be 0?
873 uint16_t InitSoc; // In mV(Q2)
874 uint16_t InitU; // In Mv(Q2) not applicable
928 uint16_t DcTol; // mV Q2
929 uint16_t DcBtcGb; // mV Q2
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dcs35l33.txt22 0, then VBST = VP. If greater than 0, the boost voltage will be 3300mV with
23 a value of 1 and will increase at a step size of 100mV until a maximum of
24 8000mV.
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
62 stage enters LDO operation. Starts as a default value of 50mV for a value
63 of 1 and increases with a step size of 50mV to a maximum of 750mV (value of
80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
81 by 100mV per step to a maximum of 5500mV.
91 1800mV with a step size of 50mV up to a maximum value of 1750mV.
92 Default is 1800mV.
[all …]
/openbmc/linux/include/dt-bindings/usb/
H A Dpd.h26 #define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
29 #define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) argument
32 #define PDO_FIXED(mv, ma, flags) \ argument
34 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
36 #define VSAFE5V 5000 /* mv units */
38 #define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
39 #define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
42 #define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) argument
43 #define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) argument
50 #define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
[all …]
/openbmc/u-boot/arch/riscv/cpu/
H A Dstart.S39 mv s0, a0
40 mv s1, a1
56 li t0, -16
58 and sp, t1, t0 /* force 16 byte alignment */
65 mv a0, sp
67 mv sp, a0
77 mv a0, zero /* a0 <-- boot_flags = 0 */
90 mv s2, a0 /* save addr_sp */
91 mv s3, a1 /* save addr of gd */
92 mv s4, a2 /* save addr of destination */
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/quilt/quilt/
H A D0001-tests-Allow-different-output-from-mv.patch4 Subject: [PATCH] tests: Allow different output from mv
6 busybox mv has different error messages: fix the test
18 @@ -16,7 +16,7 @@ What happens when refresh fails because of a permission error?
22 - >~ mv: cannot move [`']?patches/test.diff'? to [`']?patches/test.diff~'?: Permission denied
23 + >~ mv: .*: Permission denied
/openbmc/linux/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c58 u8 padding5[16];
69 } mv; member
73 u8 partition[16][3];
103 u32 partition[16][4];
289 /* mv related 6 x 128 */ in init_inter_probs()
290 memcpy(rkprobs->mv.joint, probs->mv.joint, in init_inter_probs()
291 sizeof(rkprobs->mv.joint)); in init_inter_probs()
292 memcpy(rkprobs->mv.sign, probs->mv.sign, in init_inter_probs()
293 sizeof(rkprobs->mv.sign)); in init_inter_probs()
294 memcpy(rkprobs->mv.classes, probs->mv.classes, in init_inter_probs()
[all …]
/openbmc/openbmc/meta-openembedded/meta-gnome/recipes-support/ibus/ibus/
H A D0001-makefile-don-t-gzip-the-man-pages.patch3 Date: Sun, 11 Jun 2023 16:16:35 +0900
47 mv $@.tmp $@
49 - $(AM_V_GEN) gzip -c $< > $@.tmp && mv $@.tmp $@
67 mv $@.tmp $@
69 - $(AM_V_GEN) gzip -c $< > $@.tmp && mv $@.tmp $@
85 @@ -56,20 +56,16 @@ org.freedesktop.IBus.Setup.desktop: ibus-setup.desktop
96 mv $@.tmp $@
98 - $(AM_V_GEN) gzip -c $< > $@.tmp && mv $@.tmp $@
122 mv $@.tmp $@
124 - $(AM_V_GEN) gzip -c $< > $@.tmp && mv $@.tmp $@
[all …]
/openbmc/linux/arch/riscv/kernel/
H A Dmcount.S18 addi sp, sp, -16
21 addi s0, sp, 16
40 addi sp, sp, 16
71 * value stored in -16(s0) on entry, and the s0 on return.
74 mv a0, sp
76 mv a2, a0
107 mv a1, ra
123 mv a0, ra
H A Dmcount-dyn.S20 #define ABI_A2 16
91 mv a1, ra
92 mv a3, sp
103 mv a2, s0
120 mv a1, ra
121 mv a3, sp
132 mv a2, s0
/openbmc/linux/drivers/scsi/
H A Dch.c37 #define CH_DT_MAX 16
259 if (((buffer[16] << 8) | buffer[17]) != elem) { in ch_read_element_status()
261 elem,(buffer[16] << 8) | buffer[17]); in ch_read_element_status()
265 memcpy(data,buffer+16,16); in ch_read_element_status()
296 u_char cmd[10], data[16]; in ch_readconfig()
327 (buffer[buffer[3]+16] << 8) | buffer[buffer[3]+17]; in ch_readconfig()
543 u_char data[16]; in ch_gstatus()
662 strncpy(vparams.cvp_label1,vendor_labels[0],16); in ch_ioctl()
666 strncpy(vparams.cvp_label2,vendor_labels[1],16); in ch_ioctl()
670 strncpy(vparams.cvp_label3,vendor_labels[2],16); in ch_ioctl()
[all …]
H A Dhptiop.c163 u32 inbound_head = readl(&hba->u.mv.mu->inbound_head); in mv_inbound_write()
169 memcpy_toio(&hba->u.mv.mu->inbound_q[inbound_head], &p, 8); in mv_inbound_write()
170 writel(head, &hba->u.mv.mu->inbound_head); in mv_inbound_write()
172 &hba->u.mv.regs->inbound_doorbell); in mv_inbound_write()
208 status = readl(&hba->u.mv.regs->outbound_doorbell); in iop_intr_mv()
209 writel(~status, &hba->u.mv.regs->outbound_doorbell); in iop_intr_mv()
213 msg = readl(&hba->u.mv.mu->outbound_msg); in iop_intr_mv()
222 while ((tag = mv_outbound_read(hba->u.mv.mu))) in iop_intr_mv()
323 struct hpt_iop_request_header *reqhdr = hba->u.mv.internal_req; in iop_send_sync_request_mv()
328 mv_inbound_write(hba->u.mv.internal_req_phy | in iop_send_sync_request_mv()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dboard-n8x0.c68 .num_eps = 16,
166 int mV; in n8x0_mmc_set_power_menelaus() local
179 mV = 3100; in n8x0_mmc_set_power_menelaus()
182 mV = 3000; in n8x0_mmc_set_power_menelaus()
185 mV = 2800; in n8x0_mmc_set_power_menelaus()
188 mV = 1850; in n8x0_mmc_set_power_menelaus()
193 return menelaus_set_vmmc(mV); in n8x0_mmc_set_power_menelaus()
200 mV = 3300; in n8x0_mmc_set_power_menelaus()
204 mV = 3000; in n8x0_mmc_set_power_menelaus()
208 mV = 2800; in n8x0_mmc_set_power_menelaus()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml46 - 0: 32mV/us
47 - 1: 16mV/us
48 - 2: 8mV/us
49 - 3: 4mV/us
50 - 4: 2mV/us
51 - 5: 1mV/us
52 - 6: 0.5mV/us
53 - 7: 0.25mV/us
54 Defaults to 32mV/us if not specified.
/openbmc/u-boot/board/freescale/common/
H A Dpfuze.c74 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ in pfuze_common_init()
86 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ in pfuze_common_init()
153 /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ in pfuze_common_init()
165 /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ in pfuze_common_init()
/openbmc/u-boot/include/power/
H A Dsandbox_pmic.h19 * We have only 12 significant registers, but we alloc 16 for padding.
39 SANDBOX_PMIC_REG_COUNT = 16,
67 /* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
77 /* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
82 /* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
92 /* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
/openbmc/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c42 u8 y_mode_prob[4][16];
43 u8 switch_interp_prob[4][16];
45 u8 comp_inter_prob[16];
46 u8 comp_ref_prob[16];
70 u8 uv_mode_prob[10][16];
71 u8 uv_mode_prob_padding[2][16];
73 u8 partition_prob[16][4];
112 u32 partition[16][4];
341 * @mv: mv working buffer
360 struct vdec_vp9_slice_mem mv[2]; member
[all …]
/openbmc/u-boot/board/freescale/t4qds/
H A Dt4240qds.c127 /* LSB = 4mv */ in read_voltage()
199 debug("VID: Current voltage is %d mV\n", vdd_last); in set_voltage()
272 vdd_target = vdd_override * 10; /* convert to 1/10 mV */ in adjust_vdd()
283 /* round up and divice by 10 to get a value in mV */ in adjust_vdd()
285 debug("VID: vid = %d mV\n", vdd_target); in adjust_vdd()
290 * Voltage regulator support output to 6.250mv step in adjust_vdd()
296 debug("VID: Current vid setting is (0x%x) %d mV\n", in adjust_vdd()
301 * Voltage monitor LSB is 4mv. in adjust_vdd()
309 debug("VID: Core voltage is at %d mV\n", vdd_last); in adjust_vdd()
311 * Adjust voltage to at or 8mV above target. in adjust_vdd()
[all …]
/openbmc/linux/drivers/media/v4l2-core/
H A Dv4l2-vp9.c45 { 44, 24, 16, 150, 177, 202, 33, 19, 156 }, /*left = d153*/
88 { 46, 16, 24, 136, 76, 147, 41, 64, 172 }, /*left = d117*/
101 { 68, 26, 16, 111, 141, 215, 29, 28, 28 }, /*left = d207*/
130 const u8 v4l2_vp9_kf_partition_probs[16][3] = {
136 /* 16x16 -> 8x8 */
141 /* 32x32 -> 16x16 */
281 { 3, 16, 42 },
301 { 1, 16, 28 },
594 { /* tx = 16x16 */
600 { 1, 16, 30 },
[all …]
/openbmc/u-boot/include/configs/
H A Dds414.h14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
60 /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
63 * mv-common.h should be defined after CMD configs since it used them
66 #include "mv-common.h"
87 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
93 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))

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