1837d542aSEvan Quan /* 2837d542aSEvan Quan * Copyright 2019 Advanced Micro Devices, Inc. 3837d542aSEvan Quan * 4837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10837d542aSEvan Quan * 11837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12837d542aSEvan Quan * all copies or substantial portions of the Software. 13837d542aSEvan Quan * 14837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21837d542aSEvan Quan * 22837d542aSEvan Quan */ 23837d542aSEvan Quan #ifndef __SMU11_DRIVER_IF_NAVI10_H__ 24837d542aSEvan Quan #define __SMU11_DRIVER_IF_NAVI10_H__ 25837d542aSEvan Quan 26837d542aSEvan Quan // *** IMPORTANT *** 27837d542aSEvan Quan // SMU TEAM: Always increment the interface version if 28837d542aSEvan Quan // any structure is changed in this file 29837d542aSEvan Quan // Be aware of that the version should be updated in 30837d542aSEvan Quan // smu_v11_0.h, maybe rename is also needed. 31837d542aSEvan Quan // #define SMU11_DRIVER_IF_VERSION 0x33 32837d542aSEvan Quan 33837d542aSEvan Quan #define PPTABLE_NV10_SMU_VERSION 8 34837d542aSEvan Quan 35837d542aSEvan Quan #define NUM_GFXCLK_DPM_LEVELS 16 36837d542aSEvan Quan #define NUM_SMNCLK_DPM_LEVELS 2 37837d542aSEvan Quan #define NUM_SOCCLK_DPM_LEVELS 8 38837d542aSEvan Quan #define NUM_MP0CLK_DPM_LEVELS 2 39837d542aSEvan Quan #define NUM_DCLK_DPM_LEVELS 8 40837d542aSEvan Quan #define NUM_VCLK_DPM_LEVELS 8 41837d542aSEvan Quan #define NUM_DCEFCLK_DPM_LEVELS 8 42837d542aSEvan Quan #define NUM_PHYCLK_DPM_LEVELS 8 43837d542aSEvan Quan #define NUM_DISPCLK_DPM_LEVELS 8 44837d542aSEvan Quan #define NUM_PIXCLK_DPM_LEVELS 8 45837d542aSEvan Quan #define NUM_UCLK_DPM_LEVELS 4 46837d542aSEvan Quan #define NUM_MP1CLK_DPM_LEVELS 2 47837d542aSEvan Quan #define NUM_LINK_LEVELS 2 48837d542aSEvan Quan 49837d542aSEvan Quan 50837d542aSEvan Quan #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1) 51837d542aSEvan Quan #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1) 52837d542aSEvan Quan #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1) 53837d542aSEvan Quan #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1) 54837d542aSEvan Quan #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1) 55837d542aSEvan Quan #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1) 56837d542aSEvan Quan #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1) 57837d542aSEvan Quan #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1) 58837d542aSEvan Quan #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1) 59837d542aSEvan Quan #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1) 60837d542aSEvan Quan #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1) 61837d542aSEvan Quan #define MAX_MP1CLK_DPM_LEVEL (NUM_MP1CLK_DPM_LEVELS - 1) 62837d542aSEvan Quan #define MAX_LINK_LEVEL (NUM_LINK_LEVELS - 1) 63837d542aSEvan Quan 64837d542aSEvan Quan //Gemini Modes 65837d542aSEvan Quan #define PPSMC_GeminiModeNone 0 //Single GPU board 66837d542aSEvan Quan #define PPSMC_GeminiModeMaster 1 //Master GPU on a Gemini board 67837d542aSEvan Quan #define PPSMC_GeminiModeSlave 2 //Slave GPU on a Gemini board 68837d542aSEvan Quan 69837d542aSEvan Quan // Feature Control Defines 70837d542aSEvan Quan // DPM 71837d542aSEvan Quan #define FEATURE_DPM_PREFETCHER_BIT 0 72837d542aSEvan Quan #define FEATURE_DPM_GFXCLK_BIT 1 73837d542aSEvan Quan #define FEATURE_DPM_GFX_PACE_BIT 2 74837d542aSEvan Quan #define FEATURE_DPM_UCLK_BIT 3 75837d542aSEvan Quan #define FEATURE_DPM_SOCCLK_BIT 4 76837d542aSEvan Quan #define FEATURE_DPM_MP0CLK_BIT 5 77837d542aSEvan Quan #define FEATURE_DPM_LINK_BIT 6 78837d542aSEvan Quan #define FEATURE_DPM_DCEFCLK_BIT 7 79837d542aSEvan Quan #define FEATURE_MEM_VDDCI_SCALING_BIT 8 80837d542aSEvan Quan #define FEATURE_MEM_MVDD_SCALING_BIT 9 81837d542aSEvan Quan 82837d542aSEvan Quan //Idle 83837d542aSEvan Quan #define FEATURE_DS_GFXCLK_BIT 10 84837d542aSEvan Quan #define FEATURE_DS_SOCCLK_BIT 11 85837d542aSEvan Quan #define FEATURE_DS_LCLK_BIT 12 86837d542aSEvan Quan #define FEATURE_DS_DCEFCLK_BIT 13 87837d542aSEvan Quan #define FEATURE_DS_UCLK_BIT 14 88837d542aSEvan Quan #define FEATURE_GFX_ULV_BIT 15 89837d542aSEvan Quan #define FEATURE_FW_DSTATE_BIT 16 90837d542aSEvan Quan #define FEATURE_GFXOFF_BIT 17 91837d542aSEvan Quan #define FEATURE_BACO_BIT 18 92837d542aSEvan Quan #define FEATURE_VCN_PG_BIT 19 93837d542aSEvan Quan #define FEATURE_JPEG_PG_BIT 20 94837d542aSEvan Quan #define FEATURE_USB_PG_BIT 21 95837d542aSEvan Quan #define FEATURE_RSMU_SMN_CG_BIT 22 96837d542aSEvan Quan //Throttler/Response 97837d542aSEvan Quan #define FEATURE_PPT_BIT 23 98837d542aSEvan Quan #define FEATURE_TDC_BIT 24 99837d542aSEvan Quan #define FEATURE_GFX_EDC_BIT 25 100837d542aSEvan Quan #define FEATURE_APCC_PLUS_BIT 26 101837d542aSEvan Quan #define FEATURE_GTHR_BIT 27 102837d542aSEvan Quan #define FEATURE_ACDC_BIT 28 103837d542aSEvan Quan #define FEATURE_VR0HOT_BIT 29 104837d542aSEvan Quan #define FEATURE_VR1HOT_BIT 30 105837d542aSEvan Quan #define FEATURE_FW_CTF_BIT 31 106837d542aSEvan Quan #define FEATURE_FAN_CONTROL_BIT 32 107837d542aSEvan Quan #define FEATURE_THERMAL_BIT 33 108837d542aSEvan Quan #define FEATURE_GFX_DCS_BIT 34 109837d542aSEvan Quan //VF 110837d542aSEvan Quan #define FEATURE_RM_BIT 35 111837d542aSEvan Quan #define FEATURE_LED_DISPLAY_BIT 36 112837d542aSEvan Quan //Other 113837d542aSEvan Quan #define FEATURE_GFX_SS_BIT 37 114837d542aSEvan Quan #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 115837d542aSEvan Quan #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 116837d542aSEvan Quan 117837d542aSEvan Quan #define FEATURE_MMHUB_PG_BIT 40 118837d542aSEvan Quan #define FEATURE_ATHUB_PG_BIT 41 119837d542aSEvan Quan #define FEATURE_APCC_DFLL_BIT 42 120837d542aSEvan Quan #define FEATURE_SPARE_43_BIT 43 121837d542aSEvan Quan #define FEATURE_SPARE_44_BIT 44 122837d542aSEvan Quan #define FEATURE_SPARE_45_BIT 45 123837d542aSEvan Quan #define FEATURE_SPARE_46_BIT 46 124837d542aSEvan Quan #define FEATURE_SPARE_47_BIT 47 125837d542aSEvan Quan #define FEATURE_SPARE_48_BIT 48 126837d542aSEvan Quan #define FEATURE_SPARE_49_BIT 49 127837d542aSEvan Quan #define FEATURE_SPARE_50_BIT 50 128837d542aSEvan Quan #define FEATURE_SPARE_51_BIT 51 129837d542aSEvan Quan #define FEATURE_SPARE_52_BIT 52 130837d542aSEvan Quan #define FEATURE_SPARE_53_BIT 53 131837d542aSEvan Quan #define FEATURE_SPARE_54_BIT 54 132837d542aSEvan Quan #define FEATURE_SPARE_55_BIT 55 133837d542aSEvan Quan #define FEATURE_SPARE_56_BIT 56 134837d542aSEvan Quan #define FEATURE_SPARE_57_BIT 57 135837d542aSEvan Quan #define FEATURE_SPARE_58_BIT 58 136837d542aSEvan Quan #define FEATURE_SPARE_59_BIT 59 137837d542aSEvan Quan #define FEATURE_SPARE_60_BIT 60 138837d542aSEvan Quan #define FEATURE_SPARE_61_BIT 61 139837d542aSEvan Quan #define FEATURE_SPARE_62_BIT 62 140837d542aSEvan Quan #define FEATURE_SPARE_63_BIT 63 141837d542aSEvan Quan #define NUM_FEATURES 64 142837d542aSEvan Quan 143837d542aSEvan Quan // Debug Overrides Bitmask 144837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 145837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 146837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_SOCCLK 0x00000004 147837d542aSEvan Quan #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK 0x00000008 148837d542aSEvan Quan #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK 0x00000010 149837d542aSEvan Quan #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00000020 150837d542aSEvan Quan #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK 0x00000040 151837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_SOCCLK 0x00000080 152837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK 0x00000100 153837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN 0x00000200 154837d542aSEvan Quan #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x00000400 155837d542aSEvan Quan 156837d542aSEvan Quan // VR Mapping Bit Defines 157837d542aSEvan Quan #define VR_MAPPING_VR_SELECT_MASK 0x01 158837d542aSEvan Quan #define VR_MAPPING_VR_SELECT_SHIFT 0x00 159837d542aSEvan Quan 160837d542aSEvan Quan #define VR_MAPPING_PLANE_SELECT_MASK 0x02 161837d542aSEvan Quan #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 162837d542aSEvan Quan 163837d542aSEvan Quan // PSI Bit Defines 164837d542aSEvan Quan #define PSI_SEL_VR0_PLANE0_PSI0 0x01 165837d542aSEvan Quan #define PSI_SEL_VR0_PLANE0_PSI1 0x02 166837d542aSEvan Quan #define PSI_SEL_VR0_PLANE1_PSI0 0x04 167837d542aSEvan Quan #define PSI_SEL_VR0_PLANE1_PSI1 0x08 168837d542aSEvan Quan #define PSI_SEL_VR1_PLANE0_PSI0 0x10 169837d542aSEvan Quan #define PSI_SEL_VR1_PLANE0_PSI1 0x20 170837d542aSEvan Quan #define PSI_SEL_VR1_PLANE1_PSI0 0x40 171837d542aSEvan Quan #define PSI_SEL_VR1_PLANE1_PSI1 0x80 172837d542aSEvan Quan 173837d542aSEvan Quan // Throttler Control/Status Bits 174837d542aSEvan Quan #define THROTTLER_PADDING_BIT 0 175837d542aSEvan Quan #define THROTTLER_TEMP_EDGE_BIT 1 176837d542aSEvan Quan #define THROTTLER_TEMP_HOTSPOT_BIT 2 177837d542aSEvan Quan #define THROTTLER_TEMP_MEM_BIT 3 178837d542aSEvan Quan #define THROTTLER_TEMP_VR_GFX_BIT 4 179837d542aSEvan Quan #define THROTTLER_TEMP_VR_MEM0_BIT 5 180837d542aSEvan Quan #define THROTTLER_TEMP_VR_MEM1_BIT 6 181837d542aSEvan Quan #define THROTTLER_TEMP_VR_SOC_BIT 7 182837d542aSEvan Quan #define THROTTLER_TEMP_LIQUID0_BIT 8 183837d542aSEvan Quan #define THROTTLER_TEMP_LIQUID1_BIT 9 184837d542aSEvan Quan #define THROTTLER_TEMP_PLX_BIT 10 185837d542aSEvan Quan #define THROTTLER_TEMP_SKIN_BIT 11 186837d542aSEvan Quan #define THROTTLER_TDC_GFX_BIT 12 187837d542aSEvan Quan #define THROTTLER_TDC_SOC_BIT 13 188837d542aSEvan Quan #define THROTTLER_PPT0_BIT 14 189837d542aSEvan Quan #define THROTTLER_PPT1_BIT 15 190837d542aSEvan Quan #define THROTTLER_PPT2_BIT 16 191837d542aSEvan Quan #define THROTTLER_PPT3_BIT 17 192837d542aSEvan Quan #define THROTTLER_FIT_BIT 18 193837d542aSEvan Quan #define THROTTLER_PPM_BIT 19 194837d542aSEvan Quan #define THROTTLER_APCC_BIT 20 195837d542aSEvan Quan 196837d542aSEvan Quan // FW DState Features Control Bits 197837d542aSEvan Quan #define FW_DSTATE_SOC_ULV_BIT 0 198837d542aSEvan Quan #define FW_DSTATE_G6_HSR_BIT 1 199837d542aSEvan Quan #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT 2 200837d542aSEvan Quan #define FW_DSTATE_MP0_DS_BIT 3 201837d542aSEvan Quan #define FW_DSTATE_SMN_DS_BIT 4 202837d542aSEvan Quan #define FW_DSTATE_MP1_DS_BIT 5 203837d542aSEvan Quan #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 204837d542aSEvan Quan #define FW_DSTATE_LIV_MIN_BIT 7 205837d542aSEvan Quan #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 206837d542aSEvan Quan 207837d542aSEvan Quan #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) 208837d542aSEvan Quan #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) 209837d542aSEvan Quan #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) 210837d542aSEvan Quan #define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) 211837d542aSEvan Quan #define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) 212837d542aSEvan Quan #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) 213837d542aSEvan Quan #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) 214837d542aSEvan Quan #define FW_DSTATE_LIV_MIN_MASK (1 << FW_DSTATE_LIV_MIN_BIT ) 215837d542aSEvan Quan #define FW_DSTATE_SOC_PLL_PWRDN_MASK (1 << FW_DSTATE_SOC_PLL_PWRDN_BIT ) 216837d542aSEvan Quan 217837d542aSEvan Quan //I2C Interface 218837d542aSEvan Quan 219837d542aSEvan Quan #define NUM_I2C_CONTROLLERS 8 220837d542aSEvan Quan 221837d542aSEvan Quan #define I2C_CONTROLLER_ENABLED 1 222837d542aSEvan Quan #define I2C_CONTROLLER_DISABLED 0 223837d542aSEvan Quan 224837d542aSEvan Quan #define MAX_SW_I2C_COMMANDS 8 225837d542aSEvan Quan 226837d542aSEvan Quan typedef enum { 227837d542aSEvan Quan I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 228837d542aSEvan Quan I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 229837d542aSEvan Quan I2C_CONTROLLER_PORT_COUNT, 230837d542aSEvan Quan } I2cControllerPort_e; 231837d542aSEvan Quan 232837d542aSEvan Quan typedef enum { 233837d542aSEvan Quan I2C_CONTROLLER_NAME_VR_GFX = 0, 234837d542aSEvan Quan I2C_CONTROLLER_NAME_VR_SOC, 235837d542aSEvan Quan I2C_CONTROLLER_NAME_VR_VDDCI, 236837d542aSEvan Quan I2C_CONTROLLER_NAME_VR_MVDD, 237837d542aSEvan Quan I2C_CONTROLLER_NAME_LIQUID0, 238837d542aSEvan Quan I2C_CONTROLLER_NAME_LIQUID1, 239837d542aSEvan Quan I2C_CONTROLLER_NAME_PLX, 240837d542aSEvan Quan I2C_CONTROLLER_NAME_SPARE, 241837d542aSEvan Quan I2C_CONTROLLER_NAME_COUNT, 242837d542aSEvan Quan } I2cControllerName_e; 243837d542aSEvan Quan 244837d542aSEvan Quan typedef enum { 245837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 246837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_VR_GFX, 247837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_VR_SOC, 248837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_VR_VDDCI, 249837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_VR_MVDD, 250837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_LIQUID0, 251837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_LIQUID1, 252837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_PLX, 253837d542aSEvan Quan I2C_CONTROLLER_THROTTLER_COUNT, 254837d542aSEvan Quan } I2cControllerThrottler_e; 255837d542aSEvan Quan 256837d542aSEvan Quan typedef enum { 257837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_VR_0, 258837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_VR_1, 259837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_TMP_0, 260837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_TMP_1, 261837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_SPARE_0, 262837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_SPARE_1, 263837d542aSEvan Quan I2C_CONTROLLER_PROTOCOL_COUNT, 264837d542aSEvan Quan } I2cControllerProtocol_e; 265837d542aSEvan Quan 266837d542aSEvan Quan typedef struct { 267837d542aSEvan Quan uint8_t Enabled; 268837d542aSEvan Quan uint8_t Speed; 269837d542aSEvan Quan uint8_t Padding[2]; 270837d542aSEvan Quan uint32_t SlaveAddress; 271837d542aSEvan Quan uint8_t ControllerPort; 272837d542aSEvan Quan uint8_t ControllerName; 273837d542aSEvan Quan uint8_t ThermalThrotter; 274837d542aSEvan Quan uint8_t I2cProtocol; 275837d542aSEvan Quan } I2cControllerConfig_t; 276837d542aSEvan Quan 277837d542aSEvan Quan typedef enum { 278837d542aSEvan Quan I2C_PORT_SVD_SCL = 0, 279837d542aSEvan Quan I2C_PORT_GPIO, 280837d542aSEvan Quan } I2cPort_e; 281837d542aSEvan Quan 282837d542aSEvan Quan typedef enum { 283837d542aSEvan Quan I2C_SPEED_FAST_50K = 0, //50 Kbits/s 284837d542aSEvan Quan I2C_SPEED_FAST_100K, //100 Kbits/s 285837d542aSEvan Quan I2C_SPEED_FAST_400K, //400 Kbits/s 286837d542aSEvan Quan I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 287837d542aSEvan Quan I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 288837d542aSEvan Quan I2C_SPEED_HIGH_2M, //2.3 Mbits/s 289837d542aSEvan Quan I2C_SPEED_COUNT, 290837d542aSEvan Quan } I2cSpeed_e; 291837d542aSEvan Quan 292837d542aSEvan Quan typedef enum { 293837d542aSEvan Quan I2C_CMD_READ = 0, 294837d542aSEvan Quan I2C_CMD_WRITE, 295837d542aSEvan Quan I2C_CMD_COUNT, 296837d542aSEvan Quan } I2cCmdType_e; 297837d542aSEvan Quan 298837d542aSEvan Quan #define CMDCONFIG_STOP_BIT 0 299837d542aSEvan Quan #define CMDCONFIG_RESTART_BIT 1 300837d542aSEvan Quan 301837d542aSEvan Quan #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 302837d542aSEvan Quan #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 303837d542aSEvan Quan 304837d542aSEvan Quan typedef struct { 305837d542aSEvan Quan uint8_t RegisterAddr; ////only valid for write, ignored for read 306837d542aSEvan Quan uint8_t Cmd; //Read(0) or Write(1) 307837d542aSEvan Quan uint8_t Data; //Return data for read. Data to send for write 308837d542aSEvan Quan uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command 309837d542aSEvan Quan } SwI2cCmd_t; //SW I2C Command Table 310837d542aSEvan Quan 311837d542aSEvan Quan typedef struct { 312837d542aSEvan Quan uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 313837d542aSEvan Quan uint8_t I2CSpeed; //Slow(0) or Fast(1) 314837d542aSEvan Quan uint16_t SlaveAddress; 315837d542aSEvan Quan uint8_t NumCmds; //Number of commands 316837d542aSEvan Quan uint8_t Padding[3]; 317837d542aSEvan Quan 318837d542aSEvan Quan SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 319837d542aSEvan Quan 320837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 321837d542aSEvan Quan 322837d542aSEvan Quan } SwI2cRequest_t; // SW I2C Request Table 323837d542aSEvan Quan 324837d542aSEvan Quan //D3HOT sequences 325837d542aSEvan Quan typedef enum { 326837d542aSEvan Quan BACO_SEQUENCE, 327837d542aSEvan Quan MSR_SEQUENCE, 328837d542aSEvan Quan BAMACO_SEQUENCE, 329837d542aSEvan Quan ULPS_SEQUENCE, 330837d542aSEvan Quan D3HOT_SEQUENCE_COUNT, 331837d542aSEvan Quan }D3HOTSequence_e; 332837d542aSEvan Quan 333837d542aSEvan Quan //THis is aligned with RSMU PGFSM Register Mapping 334837d542aSEvan Quan typedef enum { 335837d542aSEvan Quan PG_DYNAMIC_MODE = 0, 336837d542aSEvan Quan PG_STATIC_MODE, 337837d542aSEvan Quan } PowerGatingMode_e; 338837d542aSEvan Quan 339837d542aSEvan Quan //This is aligned with RSMU PGFSM Register Mapping 340837d542aSEvan Quan typedef enum { 341837d542aSEvan Quan PG_POWER_DOWN = 0, 342837d542aSEvan Quan PG_POWER_UP, 343837d542aSEvan Quan } PowerGatingSettings_e; 344837d542aSEvan Quan 345837d542aSEvan Quan typedef struct { 346837d542aSEvan Quan uint32_t a; // store in IEEE float format in this variable 347837d542aSEvan Quan uint32_t b; // store in IEEE float format in this variable 348837d542aSEvan Quan uint32_t c; // store in IEEE float format in this variable 349837d542aSEvan Quan } QuadraticInt_t; 350837d542aSEvan Quan 351837d542aSEvan Quan typedef struct { 352837d542aSEvan Quan uint32_t m; // store in IEEE float format in this variable 353837d542aSEvan Quan uint32_t b; // store in IEEE float format in this variable 354837d542aSEvan Quan } LinearInt_t; 355837d542aSEvan Quan 356837d542aSEvan Quan typedef struct { 357837d542aSEvan Quan uint32_t a; // store in IEEE float format in this variable 358837d542aSEvan Quan uint32_t b; // store in IEEE float format in this variable 359837d542aSEvan Quan uint32_t c; // store in IEEE float format in this variable 360837d542aSEvan Quan } DroopInt_t; 361837d542aSEvan Quan 362837d542aSEvan Quan typedef enum { 363837d542aSEvan Quan GFXCLK_SOURCE_PLL = 0, 364837d542aSEvan Quan GFXCLK_SOURCE_DFLL, 365837d542aSEvan Quan GFXCLK_SOURCE_COUNT, 366837d542aSEvan Quan } GfxclkSrc_e; 367837d542aSEvan Quan 368837d542aSEvan Quan //Only Clks that have DPM descriptors are listed here 369837d542aSEvan Quan typedef enum { 370837d542aSEvan Quan PPCLK_GFXCLK = 0, 371837d542aSEvan Quan PPCLK_SOCCLK, 372837d542aSEvan Quan PPCLK_UCLK, 373837d542aSEvan Quan PPCLK_DCLK, 374837d542aSEvan Quan PPCLK_VCLK, 375837d542aSEvan Quan PPCLK_DCEFCLK, 376837d542aSEvan Quan PPCLK_DISPCLK, 377837d542aSEvan Quan PPCLK_PIXCLK, 378837d542aSEvan Quan PPCLK_PHYCLK, 379837d542aSEvan Quan PPCLK_COUNT, 380837d542aSEvan Quan } PPCLK_e; 381837d542aSEvan Quan 382837d542aSEvan Quan typedef enum { 383837d542aSEvan Quan POWER_SOURCE_AC, 384837d542aSEvan Quan POWER_SOURCE_DC, 385837d542aSEvan Quan POWER_SOURCE_COUNT, 386837d542aSEvan Quan } POWER_SOURCE_e; 387837d542aSEvan Quan 388837d542aSEvan Quan typedef enum { 389837d542aSEvan Quan PPT_THROTTLER_PPT0, 390837d542aSEvan Quan PPT_THROTTLER_PPT1, 391837d542aSEvan Quan PPT_THROTTLER_PPT2, 392837d542aSEvan Quan PPT_THROTTLER_PPT3, 393837d542aSEvan Quan PPT_THROTTLER_COUNT 394837d542aSEvan Quan } PPT_THROTTLER_e; 395837d542aSEvan Quan 396837d542aSEvan Quan typedef enum { 397837d542aSEvan Quan VOLTAGE_MODE_AVFS = 0, 398837d542aSEvan Quan VOLTAGE_MODE_AVFS_SS, 399837d542aSEvan Quan VOLTAGE_MODE_SS, 400837d542aSEvan Quan VOLTAGE_MODE_COUNT, 401837d542aSEvan Quan } VOLTAGE_MODE_e; 402837d542aSEvan Quan 403837d542aSEvan Quan 404837d542aSEvan Quan typedef enum { 405837d542aSEvan Quan AVFS_VOLTAGE_GFX = 0, 406837d542aSEvan Quan AVFS_VOLTAGE_SOC, 407837d542aSEvan Quan AVFS_VOLTAGE_COUNT, 408837d542aSEvan Quan } AVFS_VOLTAGE_TYPE_e; 409837d542aSEvan Quan 410837d542aSEvan Quan typedef enum { 411837d542aSEvan Quan UCLK_DIV_BY_1 = 0, 412837d542aSEvan Quan UCLK_DIV_BY_2, 413837d542aSEvan Quan UCLK_DIV_BY_4, 414837d542aSEvan Quan UCLK_DIV_BY_8, 415837d542aSEvan Quan } UCLK_DIV_e; 416837d542aSEvan Quan 417837d542aSEvan Quan typedef enum { 418837d542aSEvan Quan GPIO_INT_POLARITY_ACTIVE_LOW = 0, 419837d542aSEvan Quan GPIO_INT_POLARITY_ACTIVE_HIGH, 420837d542aSEvan Quan } GpioIntPolarity_e; 421837d542aSEvan Quan 422837d542aSEvan Quan typedef enum { 423837d542aSEvan Quan MEMORY_TYPE_GDDR6 = 0, 424837d542aSEvan Quan MEMORY_TYPE_HBM, 425837d542aSEvan Quan } MemoryType_e; 426837d542aSEvan Quan 427837d542aSEvan Quan typedef enum { 428837d542aSEvan Quan PWR_CONFIG_TDP = 0, 429837d542aSEvan Quan PWR_CONFIG_TGP, 430837d542aSEvan Quan PWR_CONFIG_TCP_ESTIMATED, 431837d542aSEvan Quan PWR_CONFIG_TCP_MEASURED, 432837d542aSEvan Quan } PwrConfig_e; 433837d542aSEvan Quan 434837d542aSEvan Quan typedef struct { 435837d542aSEvan Quan uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only 436837d542aSEvan Quan uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 437837d542aSEvan Quan uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 438837d542aSEvan Quan uint8_t Padding; 439837d542aSEvan Quan LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 440837d542aSEvan Quan QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) 441837d542aSEvan Quan } DpmDescriptor_t; 442837d542aSEvan Quan 443837d542aSEvan Quan typedef enum { 444837d542aSEvan Quan TEMP_EDGE, 445837d542aSEvan Quan TEMP_HOTSPOT, 446837d542aSEvan Quan TEMP_MEM, 447837d542aSEvan Quan TEMP_VR_GFX, 448837d542aSEvan Quan TEMP_VR_MEM0, 449837d542aSEvan Quan TEMP_VR_MEM1, 450837d542aSEvan Quan TEMP_VR_SOC, 451837d542aSEvan Quan TEMP_LIQUID0, 452837d542aSEvan Quan TEMP_LIQUID1, 453837d542aSEvan Quan TEMP_PLX, 454837d542aSEvan Quan TEMP_COUNT 455837d542aSEvan Quan } TEMP_e; 456837d542aSEvan Quan 457837d542aSEvan Quan //Out of band monitor status defines 458837d542aSEvan Quan //see SPEC //gpu/doc/soc_arch/spec/feature/SMBUS/SMBUS.xlsx 459837d542aSEvan Quan #define POWER_MANAGER_CONTROLLER_NOT_RUNNING 0 460837d542aSEvan Quan #define POWER_MANAGER_CONTROLLER_RUNNING 1 461837d542aSEvan Quan 462837d542aSEvan Quan #define POWER_MANAGER_CONTROLLER_BIT 0 463837d542aSEvan Quan #define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT 8 464837d542aSEvan Quan #define GPU_DIE_TEMPERATURE_THROTTLING_BIT 9 465837d542aSEvan Quan #define HBM_DIE_TEMPERATURE_THROTTLING_BIT 10 466837d542aSEvan Quan #define TGP_THROTTLING_BIT 11 467837d542aSEvan Quan #define PCC_THROTTLING_BIT 12 468837d542aSEvan Quan #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT 13 469837d542aSEvan Quan #define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT 14 470837d542aSEvan Quan 471837d542aSEvan Quan #define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT ) 472837d542aSEvan Quan #define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_MASK (1 << MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT ) 473837d542aSEvan Quan #define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT ) 474837d542aSEvan Quan #define HBM_DIE_TEMPERATURE_THROTTLING_MASK (1 << HBM_DIE_TEMPERATURE_THROTTLING_BIT ) 475837d542aSEvan Quan #define TGP_THROTTLING_MASK (1 << TGP_THROTTLING_BIT ) 476837d542aSEvan Quan #define PCC_THROTTLING_MASK (1 << PCC_THROTTLING_BIT ) 477837d542aSEvan Quan #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK (1 << HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT ) 478837d542aSEvan Quan #define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT) 479837d542aSEvan Quan 480837d542aSEvan Quan //This structure to be DMA to SMBUS Config register space 481837d542aSEvan Quan typedef struct { 482837d542aSEvan Quan uint8_t MinorInfoVersion; 483837d542aSEvan Quan uint8_t MajorInfoVersion; 484837d542aSEvan Quan uint8_t TableSize; 485837d542aSEvan Quan uint8_t Reserved; 486837d542aSEvan Quan 487837d542aSEvan Quan uint8_t Reserved1; 488837d542aSEvan Quan uint8_t RevID; 489837d542aSEvan Quan uint16_t DeviceID; 490837d542aSEvan Quan 491837d542aSEvan Quan uint16_t DieTemperatureLimit; 492837d542aSEvan Quan uint16_t FanTargetTemperature; 493837d542aSEvan Quan 494837d542aSEvan Quan uint16_t MemoryTemperatureLimit; 495837d542aSEvan Quan uint16_t MemoryTemperatureLimit1; 496837d542aSEvan Quan 497837d542aSEvan Quan uint16_t TGP; 498837d542aSEvan Quan uint16_t CardPower; 499837d542aSEvan Quan 500837d542aSEvan Quan uint32_t DieTemperatureRegisterOffset; 501837d542aSEvan Quan 502837d542aSEvan Quan uint32_t Reserved2; 503837d542aSEvan Quan 504837d542aSEvan Quan uint32_t Reserved3; 505837d542aSEvan Quan 506837d542aSEvan Quan uint32_t Status; 507837d542aSEvan Quan 508837d542aSEvan Quan uint16_t DieTemperature; 509837d542aSEvan Quan uint16_t CurrentMemoryTemperature; 510837d542aSEvan Quan 511837d542aSEvan Quan uint16_t MemoryTemperature; 512837d542aSEvan Quan uint8_t MemoryHotspotPosition; 513837d542aSEvan Quan uint8_t Reserved4; 514837d542aSEvan Quan 515837d542aSEvan Quan uint32_t BoardLevelEnergyAccumulator; 516837d542aSEvan Quan } OutOfBandMonitor_t; 517837d542aSEvan Quan 518*f989fa29SJonathan Gray #pragma pack(push, 1) 519837d542aSEvan Quan typedef struct { 520837d542aSEvan Quan uint32_t Version; 521837d542aSEvan Quan 522837d542aSEvan Quan // SECTION: Feature Enablement 523837d542aSEvan Quan uint32_t FeaturesToRun[2]; 524837d542aSEvan Quan 525837d542aSEvan Quan // SECTION: Infrastructure Limits 526837d542aSEvan Quan uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; 527837d542aSEvan Quan uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; 528837d542aSEvan Quan uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; 529837d542aSEvan Quan uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; 530837d542aSEvan Quan 531837d542aSEvan Quan uint16_t TdcLimitSoc; // Amps 532837d542aSEvan Quan uint16_t TdcLimitSocTau; // Time constant of LPF in ms 533837d542aSEvan Quan uint16_t TdcLimitGfx; // Amps 534837d542aSEvan Quan uint16_t TdcLimitGfxTau; // Time constant of LPF in ms 535837d542aSEvan Quan 536837d542aSEvan Quan uint16_t TedgeLimit; // Celcius 537837d542aSEvan Quan uint16_t ThotspotLimit; // Celcius 538837d542aSEvan Quan uint16_t TmemLimit; // Celcius 539837d542aSEvan Quan uint16_t Tvr_gfxLimit; // Celcius 540837d542aSEvan Quan uint16_t Tvr_mem0Limit; // Celcius 541837d542aSEvan Quan uint16_t Tvr_mem1Limit; // Celcius 542837d542aSEvan Quan uint16_t Tvr_socLimit; // Celcius 543837d542aSEvan Quan uint16_t Tliquid0Limit; // Celcius 544837d542aSEvan Quan uint16_t Tliquid1Limit; // Celcius 545837d542aSEvan Quan uint16_t TplxLimit; // Celcius 546837d542aSEvan Quan uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) 547837d542aSEvan Quan 548837d542aSEvan Quan uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold 549837d542aSEvan Quan uint16_t PpmTemperatureThreshold; 550837d542aSEvan Quan 551837d542aSEvan Quan // SECTION: Throttler settings 552837d542aSEvan Quan uint32_t ThrottlerControlMask; // See Throtter masks defines 553837d542aSEvan Quan 554837d542aSEvan Quan // SECTION: FW DSTATE Settings 555837d542aSEvan Quan uint32_t FwDStateMask; // See FW DState masks defines 556837d542aSEvan Quan 557837d542aSEvan Quan // SECTION: ULV Settings 558837d542aSEvan Quan uint16_t UlvVoltageOffsetSoc; // In mV(Q2) 559837d542aSEvan Quan uint16_t UlvVoltageOffsetGfx; // In mV(Q2) 560837d542aSEvan Quan 561837d542aSEvan Quan uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events 562837d542aSEvan Quan uint8_t paddingRlcUlvParams[3]; 563837d542aSEvan Quan 564837d542aSEvan Quan uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 565837d542aSEvan Quan uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. 566837d542aSEvan Quan uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV 567837d542aSEvan Quan uint8_t Padding234; 568837d542aSEvan Quan 569837d542aSEvan Quan uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode 570837d542aSEvan Quan uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode 571837d542aSEvan Quan 572837d542aSEvan Quan 573837d542aSEvan Quan // SECTION: Voltage Control Parameters 574837d542aSEvan Quan uint16_t MinVoltageGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX 575837d542aSEvan Quan uint16_t MinVoltageSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC 576837d542aSEvan Quan uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX 577837d542aSEvan Quan uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC 578837d542aSEvan Quan 579837d542aSEvan Quan uint16_t LoadLineResistanceGfx; // In mOhms with 8 fractional bits 580837d542aSEvan Quan uint16_t LoadLineResistanceSoc; // In mOhms with 8 fractional bits 581837d542aSEvan Quan 582837d542aSEvan Quan //SECTION: DPM Config 1 583837d542aSEvan Quan DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 584837d542aSEvan Quan 585837d542aSEvan Quan uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 586837d542aSEvan Quan uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 587837d542aSEvan Quan uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 588837d542aSEvan Quan uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 589837d542aSEvan Quan uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 590837d542aSEvan Quan uint16_t FreqTableDcefclk [NUM_DCEFCLK_DPM_LEVELS ]; // In MHz 591837d542aSEvan Quan uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 592837d542aSEvan Quan uint16_t FreqTablePixclk [NUM_PIXCLK_DPM_LEVELS ]; // In MHz 593837d542aSEvan Quan uint16_t FreqTablePhyclk [NUM_PHYCLK_DPM_LEVELS ]; // In MHz 594837d542aSEvan Quan uint32_t Paddingclks[16]; 595837d542aSEvan Quan 596837d542aSEvan Quan uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 597837d542aSEvan Quan uint16_t Padding8_Clks; 598837d542aSEvan Quan 599837d542aSEvan Quan uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 600837d542aSEvan Quan 601837d542aSEvan Quan // SECTION: DPM Config 2 602837d542aSEvan Quan uint16_t Mp0clkFreq [NUM_MP0CLK_DPM_LEVELS]; // in MHz 603837d542aSEvan Quan uint16_t Mp0DpmVoltage [NUM_MP0CLK_DPM_LEVELS]; // mV(Q2) 604837d542aSEvan Quan uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 605837d542aSEvan Quan uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 606837d542aSEvan Quan // GFXCLK DPM 607837d542aSEvan Quan uint16_t GfxclkFgfxoffEntry; // in Mhz 608837d542aSEvan Quan uint16_t GfxclkFinit; // in Mhz 609837d542aSEvan Quan uint16_t GfxclkFidle; // in MHz 610837d542aSEvan Quan uint16_t GfxclkSlewRate; // for PLL babystepping??? 611837d542aSEvan Quan uint16_t GfxclkFopt; // in Mhz 612837d542aSEvan Quan uint8_t Padding567[2]; 613837d542aSEvan Quan uint16_t GfxclkDsMaxFreq; // in MHz 614837d542aSEvan Quan uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL 615837d542aSEvan Quan uint8_t Padding456; 616837d542aSEvan Quan 617837d542aSEvan Quan // UCLK section 618837d542aSEvan Quan uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only 619837d542aSEvan Quan uint8_t paddingUclk[3]; 620837d542aSEvan Quan 621837d542aSEvan Quan uint8_t MemoryType; // 0-GDDR6, 1-HBM 622837d542aSEvan Quan uint8_t MemoryChannels; 623837d542aSEvan Quan uint8_t PaddingMem[2]; 624837d542aSEvan Quan 625837d542aSEvan Quan // Link DPM Settings 626837d542aSEvan Quan uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 627837d542aSEvan Quan uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 628837d542aSEvan Quan uint16_t LclkFreq[NUM_LINK_LEVELS]; 629837d542aSEvan Quan 630837d542aSEvan Quan // GFXCLK Thermal DPM (formerly 'Boost' Settings) 631837d542aSEvan Quan uint16_t EnableTdpm; 632837d542aSEvan Quan uint16_t TdpmHighHystTemperature; 633837d542aSEvan Quan uint16_t TdpmLowHystTemperature; 634837d542aSEvan Quan uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. 635837d542aSEvan Quan 636837d542aSEvan Quan // SECTION: Fan Control 637837d542aSEvan Quan uint16_t FanStopTemp; //Celcius 638837d542aSEvan Quan uint16_t FanStartTemp; //Celcius 639837d542aSEvan Quan 640837d542aSEvan Quan uint16_t FanGainEdge; 641837d542aSEvan Quan uint16_t FanGainHotspot; 642837d542aSEvan Quan uint16_t FanGainLiquid0; 643837d542aSEvan Quan uint16_t FanGainLiquid1; 644837d542aSEvan Quan uint16_t FanGainVrGfx; 645837d542aSEvan Quan uint16_t FanGainVrSoc; 646837d542aSEvan Quan uint16_t FanGainVrMem0; 647837d542aSEvan Quan uint16_t FanGainVrMem1; 648837d542aSEvan Quan uint16_t FanGainPlx; 649837d542aSEvan Quan uint16_t FanGainMem; 650837d542aSEvan Quan uint16_t FanPwmMin; 651837d542aSEvan Quan uint16_t FanAcousticLimitRpm; 652837d542aSEvan Quan uint16_t FanThrottlingRpm; 653837d542aSEvan Quan uint16_t FanMaximumRpm; 654837d542aSEvan Quan uint16_t FanTargetTemperature; 655837d542aSEvan Quan uint16_t FanTargetGfxclk; 656837d542aSEvan Quan uint8_t FanTempInputSelect; 657837d542aSEvan Quan uint8_t FanPadding; 658837d542aSEvan Quan uint8_t FanZeroRpmEnable; 659837d542aSEvan Quan uint8_t FanTachEdgePerRev; 660837d542aSEvan Quan //uint8_t padding8_Fan[2]; 661837d542aSEvan Quan 662837d542aSEvan Quan // The following are AFC override parameters. Leave at 0 to use FW defaults. 663837d542aSEvan Quan int16_t FuzzyFan_ErrorSetDelta; 664837d542aSEvan Quan int16_t FuzzyFan_ErrorRateSetDelta; 665837d542aSEvan Quan int16_t FuzzyFan_PwmSetDelta; 666837d542aSEvan Quan uint16_t FuzzyFan_Reserved; 667837d542aSEvan Quan 668837d542aSEvan Quan 669837d542aSEvan Quan // SECTION: AVFS 670837d542aSEvan Quan // Overrides 671837d542aSEvan Quan uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 672837d542aSEvan Quan uint8_t Padding8_Avfs[2]; 673837d542aSEvan Quan 674837d542aSEvan Quan QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve 675837d542aSEvan Quan DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb 676837d542aSEvan Quan DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb 677837d542aSEvan Quan DroopInt_t dBtcGbSoc; // GHz->V BtcGb 678837d542aSEvan Quan LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V 679837d542aSEvan Quan 680837d542aSEvan Quan QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V 681837d542aSEvan Quan 682837d542aSEvan Quan uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 683837d542aSEvan Quan 684837d542aSEvan Quan uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 685837d542aSEvan Quan uint8_t Padding8_GfxBtc[2]; 686837d542aSEvan Quan 687837d542aSEvan Quan uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; // mV Q2 688837d542aSEvan Quan uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 689837d542aSEvan Quan 690837d542aSEvan Quan // SECTION: Advanced Options 691837d542aSEvan Quan uint32_t DebugOverrides; 692837d542aSEvan Quan QuadraticInt_t ReservedEquation0; 693837d542aSEvan Quan QuadraticInt_t ReservedEquation1; 694837d542aSEvan Quan QuadraticInt_t ReservedEquation2; 695837d542aSEvan Quan QuadraticInt_t ReservedEquation3; 696837d542aSEvan Quan 697837d542aSEvan Quan // Total Power configuration, use defines from PwrConfig_e 698837d542aSEvan Quan uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured 699837d542aSEvan Quan uint8_t TotalPowerSpare1; 700837d542aSEvan Quan uint16_t TotalPowerSpare2; 701837d542aSEvan Quan 702837d542aSEvan Quan // APCC Settings 703837d542aSEvan Quan uint16_t PccThresholdLow; 704837d542aSEvan Quan uint16_t PccThresholdHigh; 705837d542aSEvan Quan uint32_t MGpuFanBoostLimitRpm; 706837d542aSEvan Quan uint32_t PaddingAPCC[5]; 707837d542aSEvan Quan 708837d542aSEvan Quan // Temperature Dependent Vmin 709837d542aSEvan Quan uint16_t VDDGFX_TVmin; //Celcius 710837d542aSEvan Quan uint16_t VDDSOC_TVmin; //Celcius 711837d542aSEvan Quan uint16_t VDDGFX_Vmin_HiTemp; // mV Q2 712837d542aSEvan Quan uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 713837d542aSEvan Quan uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 714837d542aSEvan Quan uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 715837d542aSEvan Quan 716837d542aSEvan Quan uint16_t VDDGFX_TVminHystersis; // Celcius 717837d542aSEvan Quan uint16_t VDDSOC_TVminHystersis; // Celcius 718837d542aSEvan Quan 719837d542aSEvan Quan // BTC Setting 720837d542aSEvan Quan uint32_t BtcConfig; 721837d542aSEvan Quan 722837d542aSEvan Quan uint16_t SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2 723837d542aSEvan Quan uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; 724837d542aSEvan Quan 725837d542aSEvan Quan // SECTION: Board Reserved 726837d542aSEvan Quan uint32_t Reserved[8]; 727837d542aSEvan Quan 728837d542aSEvan Quan // SECTION: BOARD PARAMETERS 729837d542aSEvan Quan // I2C Control 730837d542aSEvan Quan I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 731837d542aSEvan Quan 732837d542aSEvan Quan // SVI2 Board Parameters 733837d542aSEvan Quan uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 734837d542aSEvan Quan uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 735837d542aSEvan Quan 736837d542aSEvan Quan uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 737837d542aSEvan Quan uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 738837d542aSEvan Quan uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 739837d542aSEvan Quan uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 740837d542aSEvan Quan 741837d542aSEvan Quan uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 742837d542aSEvan Quan uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 743837d542aSEvan Quan uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 744837d542aSEvan Quan uint8_t Padding8_V; 745837d542aSEvan Quan 746837d542aSEvan Quan // Telemetry Settings 747837d542aSEvan Quan uint16_t GfxMaxCurrent; // in Amps 748837d542aSEvan Quan int8_t GfxOffset; // in Amps 749837d542aSEvan Quan uint8_t Padding_TelemetryGfx; 750837d542aSEvan Quan 751837d542aSEvan Quan uint16_t SocMaxCurrent; // in Amps 752837d542aSEvan Quan int8_t SocOffset; // in Amps 753837d542aSEvan Quan uint8_t Padding_TelemetrySoc; 754837d542aSEvan Quan 755837d542aSEvan Quan uint16_t Mem0MaxCurrent; // in Amps 756837d542aSEvan Quan int8_t Mem0Offset; // in Amps 757837d542aSEvan Quan uint8_t Padding_TelemetryMem0; 758837d542aSEvan Quan 759837d542aSEvan Quan uint16_t Mem1MaxCurrent; // in Amps 760837d542aSEvan Quan int8_t Mem1Offset; // in Amps 761837d542aSEvan Quan uint8_t Padding_TelemetryMem1; 762837d542aSEvan Quan 763837d542aSEvan Quan // GPIO Settings 764837d542aSEvan Quan uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 765837d542aSEvan Quan uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 766837d542aSEvan Quan uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 767837d542aSEvan Quan uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 768837d542aSEvan Quan 769837d542aSEvan Quan uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 770837d542aSEvan Quan uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 771837d542aSEvan Quan uint8_t GthrGpio; // GPIO pin configured for GTHR Event 772837d542aSEvan Quan uint8_t GthrPolarity; // replace GPIO polarity for GTHR 773837d542aSEvan Quan 774837d542aSEvan Quan // LED Display Settings 775837d542aSEvan Quan uint8_t LedPin0; // GPIO number for LedPin[0] 776837d542aSEvan Quan uint8_t LedPin1; // GPIO number for LedPin[1] 777837d542aSEvan Quan uint8_t LedPin2; // GPIO number for LedPin[2] 778837d542aSEvan Quan uint8_t padding8_4; 779837d542aSEvan Quan 780837d542aSEvan Quan // GFXCLK PLL Spread Spectrum 781837d542aSEvan Quan uint8_t PllGfxclkSpreadEnabled; // on or off 782837d542aSEvan Quan uint8_t PllGfxclkSpreadPercent; // Q4.4 783837d542aSEvan Quan uint16_t PllGfxclkSpreadFreq; // kHz 784837d542aSEvan Quan 785837d542aSEvan Quan // GFXCLK DFLL Spread Spectrum 786837d542aSEvan Quan uint8_t DfllGfxclkSpreadEnabled; // on or off 787837d542aSEvan Quan uint8_t DfllGfxclkSpreadPercent; // Q4.4 788837d542aSEvan Quan uint16_t DfllGfxclkSpreadFreq; // kHz 789837d542aSEvan Quan 790837d542aSEvan Quan // UCLK Spread Spectrum 791837d542aSEvan Quan uint8_t UclkSpreadEnabled; // on or off 792837d542aSEvan Quan uint8_t UclkSpreadPercent; // Q4.4 793837d542aSEvan Quan uint16_t UclkSpreadFreq; // kHz 794837d542aSEvan Quan 795837d542aSEvan Quan // SOCCLK Spread Spectrum 796837d542aSEvan Quan uint8_t SoclkSpreadEnabled; // on or off 797837d542aSEvan Quan uint8_t SocclkSpreadPercent; // Q4.4 798837d542aSEvan Quan uint16_t SocclkSpreadFreq; // kHz 799837d542aSEvan Quan 800837d542aSEvan Quan // Total board power 801837d542aSEvan Quan uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 802837d542aSEvan Quan uint16_t BoardPadding; 803837d542aSEvan Quan 804837d542aSEvan Quan // Mvdd Svi2 Div Ratio Setting 805837d542aSEvan Quan uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 806837d542aSEvan Quan 807837d542aSEvan Quan uint8_t RenesesLoadLineEnabled; 808837d542aSEvan Quan uint8_t GfxLoadlineResistance; 809837d542aSEvan Quan uint8_t SocLoadlineResistance; 810837d542aSEvan Quan uint8_t Padding8_Loadline; 811837d542aSEvan Quan 812837d542aSEvan Quan uint32_t BoardReserved[8]; 813837d542aSEvan Quan 814837d542aSEvan Quan // Padding for MMHUB - do not modify this 815837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 816837d542aSEvan Quan 817837d542aSEvan Quan } PPTable_t; 818*f989fa29SJonathan Gray #pragma pack(pop) 819837d542aSEvan Quan 820837d542aSEvan Quan typedef struct { 821837d542aSEvan Quan // Time constant parameters for clock averages in ms 822837d542aSEvan Quan uint16_t GfxclkAverageLpfTau; 823837d542aSEvan Quan uint16_t SocclkAverageLpfTau; 824837d542aSEvan Quan uint16_t UclkAverageLpfTau; 825837d542aSEvan Quan uint16_t GfxActivityLpfTau; 826837d542aSEvan Quan uint16_t UclkActivityLpfTau; 827837d542aSEvan Quan uint16_t SocketPowerLpfTau; 828837d542aSEvan Quan 829837d542aSEvan Quan // Padding - ignore 830837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 831837d542aSEvan Quan } DriverSmuConfig_t; 832837d542aSEvan Quan 833837d542aSEvan Quan typedef struct { 834837d542aSEvan Quan 835837d542aSEvan Quan uint16_t GfxclkFmin; // MHz 836837d542aSEvan Quan uint16_t GfxclkFmax; // MHz 837837d542aSEvan Quan uint16_t GfxclkFreq1; // MHz 838837d542aSEvan Quan uint16_t GfxclkVolt1; // mV (Q2) 839837d542aSEvan Quan uint16_t GfxclkFreq2; // MHz 840837d542aSEvan Quan uint16_t GfxclkVolt2; // mV (Q2) 841837d542aSEvan Quan uint16_t GfxclkFreq3; // MHz 842837d542aSEvan Quan uint16_t GfxclkVolt3; // mV (Q2) 843837d542aSEvan Quan uint16_t UclkFmax; // MHz 844837d542aSEvan Quan int16_t OverDrivePct; // % 845837d542aSEvan Quan uint16_t FanMaximumRpm; 846837d542aSEvan Quan uint16_t FanMinimumPwm; 847837d542aSEvan Quan uint16_t FanTargetTemperature; // Degree Celcius 848837d542aSEvan Quan uint16_t FanMode; 849837d542aSEvan Quan uint16_t FanMaxPwm; 850837d542aSEvan Quan uint16_t FanMinPwm; 851837d542aSEvan Quan uint16_t FanMaxTemp; // Degree Celcius 852837d542aSEvan Quan uint16_t FanMinTemp; // Degree Celcius 853837d542aSEvan Quan uint16_t MaxOpTemp; // Degree Celcius 854837d542aSEvan Quan uint16_t FanZeroRpmEnable; 855837d542aSEvan Quan 856837d542aSEvan Quan uint32_t MmHubPadding[6]; // SMU internal use 857837d542aSEvan Quan 858837d542aSEvan Quan } OverDriveTable_t; 859837d542aSEvan Quan 860837d542aSEvan Quan typedef struct { 861837d542aSEvan Quan uint16_t CurrClock[PPCLK_COUNT]; 862837d542aSEvan Quan uint16_t AverageGfxclkFrequency; 863837d542aSEvan Quan uint16_t AverageSocclkFrequency; 864837d542aSEvan Quan uint16_t AverageUclkFrequency ; 865837d542aSEvan Quan uint16_t AverageGfxActivity ; 866837d542aSEvan Quan uint16_t AverageUclkActivity ; 867837d542aSEvan Quan uint8_t CurrSocVoltageOffset ; 868837d542aSEvan Quan uint8_t CurrGfxVoltageOffset ; 869837d542aSEvan Quan uint8_t CurrMemVidOffset ; 870837d542aSEvan Quan uint8_t Padding8 ; 871837d542aSEvan Quan uint16_t AverageSocketPower ; 872837d542aSEvan Quan uint16_t TemperatureEdge ; 873837d542aSEvan Quan uint16_t TemperatureHotspot ; 874837d542aSEvan Quan uint16_t TemperatureMem ; 875837d542aSEvan Quan uint16_t TemperatureVrGfx ; 876837d542aSEvan Quan uint16_t TemperatureVrMem0 ; 877837d542aSEvan Quan uint16_t TemperatureVrMem1 ; 878837d542aSEvan Quan uint16_t TemperatureVrSoc ; 879837d542aSEvan Quan uint16_t TemperatureLiquid0 ; 880837d542aSEvan Quan uint16_t TemperatureLiquid1 ; 881837d542aSEvan Quan uint16_t TemperaturePlx ; 882837d542aSEvan Quan uint16_t Padding16 ; 883837d542aSEvan Quan uint32_t ThrottlerStatus ; 884837d542aSEvan Quan 885837d542aSEvan Quan uint8_t LinkDpmLevel; 886837d542aSEvan Quan uint8_t Padding8_2; 887837d542aSEvan Quan uint16_t CurrFanSpeed; 888837d542aSEvan Quan 889837d542aSEvan Quan // Padding - ignore 890837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 891837d542aSEvan Quan } SmuMetrics_legacy_t; 892837d542aSEvan Quan 893837d542aSEvan Quan typedef struct { 894837d542aSEvan Quan uint16_t CurrClock[PPCLK_COUNT]; 895837d542aSEvan Quan uint16_t AverageGfxclkFrequencyPostDs; 896837d542aSEvan Quan uint16_t AverageSocclkFrequency; 897837d542aSEvan Quan uint16_t AverageUclkFrequencyPostDs; 898837d542aSEvan Quan uint16_t AverageGfxActivity ; 899837d542aSEvan Quan uint16_t AverageUclkActivity ; 900837d542aSEvan Quan uint8_t CurrSocVoltageOffset ; 901837d542aSEvan Quan uint8_t CurrGfxVoltageOffset ; 902837d542aSEvan Quan uint8_t CurrMemVidOffset ; 903837d542aSEvan Quan uint8_t Padding8 ; 904837d542aSEvan Quan uint16_t AverageSocketPower ; 905837d542aSEvan Quan uint16_t TemperatureEdge ; 906837d542aSEvan Quan uint16_t TemperatureHotspot ; 907837d542aSEvan Quan uint16_t TemperatureMem ; 908837d542aSEvan Quan uint16_t TemperatureVrGfx ; 909837d542aSEvan Quan uint16_t TemperatureVrMem0 ; 910837d542aSEvan Quan uint16_t TemperatureVrMem1 ; 911837d542aSEvan Quan uint16_t TemperatureVrSoc ; 912837d542aSEvan Quan uint16_t TemperatureLiquid0 ; 913837d542aSEvan Quan uint16_t TemperatureLiquid1 ; 914837d542aSEvan Quan uint16_t TemperaturePlx ; 915837d542aSEvan Quan uint16_t Padding16 ; 916837d542aSEvan Quan uint32_t ThrottlerStatus ; 917837d542aSEvan Quan 918837d542aSEvan Quan uint8_t LinkDpmLevel; 919837d542aSEvan Quan uint8_t Padding8_2; 920837d542aSEvan Quan uint16_t CurrFanSpeed; 921837d542aSEvan Quan 922837d542aSEvan Quan uint16_t AverageGfxclkFrequencyPreDs; 923837d542aSEvan Quan uint16_t AverageUclkFrequencyPreDs; 924837d542aSEvan Quan uint8_t PcieRate; 925837d542aSEvan Quan uint8_t PcieWidth; 926837d542aSEvan Quan uint8_t Padding8_3[2]; 927837d542aSEvan Quan 928837d542aSEvan Quan // Padding - ignore 929837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 930837d542aSEvan Quan } SmuMetrics_t; 931837d542aSEvan Quan 932837d542aSEvan Quan typedef struct { 933837d542aSEvan Quan uint16_t CurrClock[PPCLK_COUNT]; 934837d542aSEvan Quan uint16_t AverageGfxclkFrequency; 935837d542aSEvan Quan uint16_t AverageSocclkFrequency; 936837d542aSEvan Quan uint16_t AverageUclkFrequency ; 937837d542aSEvan Quan uint16_t AverageGfxActivity ; 938837d542aSEvan Quan uint16_t AverageUclkActivity ; 939837d542aSEvan Quan uint8_t CurrSocVoltageOffset ; 940837d542aSEvan Quan uint8_t CurrGfxVoltageOffset ; 941837d542aSEvan Quan uint8_t CurrMemVidOffset ; 942837d542aSEvan Quan uint8_t Padding8 ; 943837d542aSEvan Quan uint16_t AverageSocketPower ; 944837d542aSEvan Quan uint16_t TemperatureEdge ; 945837d542aSEvan Quan uint16_t TemperatureHotspot ; 946837d542aSEvan Quan uint16_t TemperatureMem ; 947837d542aSEvan Quan uint16_t TemperatureVrGfx ; 948837d542aSEvan Quan uint16_t TemperatureVrMem0 ; 949837d542aSEvan Quan uint16_t TemperatureVrMem1 ; 950837d542aSEvan Quan uint16_t TemperatureVrSoc ; 951837d542aSEvan Quan uint16_t TemperatureLiquid0 ; 952837d542aSEvan Quan uint16_t TemperatureLiquid1 ; 953837d542aSEvan Quan uint16_t TemperaturePlx ; 954837d542aSEvan Quan uint16_t Padding16 ; 955837d542aSEvan Quan uint32_t ThrottlerStatus ; 956837d542aSEvan Quan 957837d542aSEvan Quan uint8_t LinkDpmLevel; 958837d542aSEvan Quan uint8_t Padding8_2; 959837d542aSEvan Quan uint16_t CurrFanSpeed; 960837d542aSEvan Quan 961837d542aSEvan Quan uint32_t EnergyAccumulator; 962837d542aSEvan Quan uint16_t AverageVclkFrequency ; 963837d542aSEvan Quan uint16_t AverageDclkFrequency ; 964837d542aSEvan Quan uint16_t VcnActivityPercentage ; 965837d542aSEvan Quan uint16_t padding16_2; 966837d542aSEvan Quan 967837d542aSEvan Quan // Padding - ignore 968837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 969837d542aSEvan Quan } SmuMetrics_NV12_legacy_t; 970837d542aSEvan Quan 971837d542aSEvan Quan typedef struct { 972837d542aSEvan Quan uint16_t CurrClock[PPCLK_COUNT]; 973837d542aSEvan Quan uint16_t AverageGfxclkFrequencyPostDs; 974837d542aSEvan Quan uint16_t AverageSocclkFrequency; 975837d542aSEvan Quan uint16_t AverageUclkFrequencyPostDs; 976837d542aSEvan Quan uint16_t AverageGfxActivity ; 977837d542aSEvan Quan uint16_t AverageUclkActivity ; 978837d542aSEvan Quan uint8_t CurrSocVoltageOffset ; 979837d542aSEvan Quan uint8_t CurrGfxVoltageOffset ; 980837d542aSEvan Quan uint8_t CurrMemVidOffset ; 981837d542aSEvan Quan uint8_t Padding8 ; 982837d542aSEvan Quan uint16_t AverageSocketPower ; 983837d542aSEvan Quan uint16_t TemperatureEdge ; 984837d542aSEvan Quan uint16_t TemperatureHotspot ; 985837d542aSEvan Quan uint16_t TemperatureMem ; 986837d542aSEvan Quan uint16_t TemperatureVrGfx ; 987837d542aSEvan Quan uint16_t TemperatureVrMem0 ; 988837d542aSEvan Quan uint16_t TemperatureVrMem1 ; 989837d542aSEvan Quan uint16_t TemperatureVrSoc ; 990837d542aSEvan Quan uint16_t TemperatureLiquid0 ; 991837d542aSEvan Quan uint16_t TemperatureLiquid1 ; 992837d542aSEvan Quan uint16_t TemperaturePlx ; 993837d542aSEvan Quan uint16_t Padding16 ; 994837d542aSEvan Quan uint32_t ThrottlerStatus ; 995837d542aSEvan Quan 996837d542aSEvan Quan uint8_t LinkDpmLevel; 997837d542aSEvan Quan uint8_t Padding8_2; 998837d542aSEvan Quan uint16_t CurrFanSpeed; 999837d542aSEvan Quan 1000837d542aSEvan Quan uint16_t AverageVclkFrequency ; 1001837d542aSEvan Quan uint16_t AverageDclkFrequency ; 1002837d542aSEvan Quan uint16_t VcnActivityPercentage ; 1003837d542aSEvan Quan uint16_t AverageGfxclkFrequencyPreDs; 1004837d542aSEvan Quan uint16_t AverageUclkFrequencyPreDs; 1005837d542aSEvan Quan uint8_t PcieRate; 1006837d542aSEvan Quan uint8_t PcieWidth; 1007837d542aSEvan Quan 1008837d542aSEvan Quan uint32_t Padding32_1; 1009837d542aSEvan Quan uint64_t EnergyAccumulator; 1010837d542aSEvan Quan 1011837d542aSEvan Quan // Padding - ignore 1012837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1013837d542aSEvan Quan } SmuMetrics_NV12_t; 1014837d542aSEvan Quan 1015837d542aSEvan Quan typedef union SmuMetrics { 1016837d542aSEvan Quan SmuMetrics_legacy_t nv10_legacy_metrics; 1017837d542aSEvan Quan SmuMetrics_t nv10_metrics; 1018837d542aSEvan Quan SmuMetrics_NV12_legacy_t nv12_legacy_metrics; 1019837d542aSEvan Quan SmuMetrics_NV12_t nv12_metrics; 1020837d542aSEvan Quan } SmuMetrics_NV1X_t; 1021837d542aSEvan Quan 1022837d542aSEvan Quan typedef struct { 1023837d542aSEvan Quan uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) 1024837d542aSEvan Quan uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) 1025837d542aSEvan Quan uint16_t MinUclk; 1026837d542aSEvan Quan uint16_t MaxUclk; 1027837d542aSEvan Quan 1028837d542aSEvan Quan uint8_t WmSetting; 1029837d542aSEvan Quan uint8_t Padding[3]; 1030837d542aSEvan Quan 1031837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1032837d542aSEvan Quan } WatermarkRowGeneric_t; 1033837d542aSEvan Quan 1034837d542aSEvan Quan #define NUM_WM_RANGES 4 1035837d542aSEvan Quan 1036837d542aSEvan Quan typedef enum { 1037837d542aSEvan Quan WM_SOCCLK = 0, 1038837d542aSEvan Quan WM_DCEFCLK, 1039837d542aSEvan Quan WM_COUNT, 1040837d542aSEvan Quan } WM_CLOCK_e; 1041837d542aSEvan Quan 1042837d542aSEvan Quan typedef struct { 1043837d542aSEvan Quan // Watermarks 1044837d542aSEvan Quan WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 1045837d542aSEvan Quan 1046837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1047837d542aSEvan Quan } Watermarks_t; 1048837d542aSEvan Quan 1049837d542aSEvan Quan typedef struct { 1050837d542aSEvan Quan uint16_t avgPsmCount[28]; 1051837d542aSEvan Quan uint16_t minPsmCount[28]; 1052837d542aSEvan Quan float avgPsmVoltage[28]; 1053837d542aSEvan Quan float minPsmVoltage[28]; 1054837d542aSEvan Quan 1055837d542aSEvan Quan uint32_t MmHubPadding[32]; // SMU internal use 1056837d542aSEvan Quan } AvfsDebugTable_t_NV14; 1057837d542aSEvan Quan 1058837d542aSEvan Quan typedef struct { 1059837d542aSEvan Quan uint16_t avgPsmCount[36]; 1060837d542aSEvan Quan uint16_t minPsmCount[36]; 1061837d542aSEvan Quan float avgPsmVoltage[36]; 1062837d542aSEvan Quan float minPsmVoltage[36]; 1063837d542aSEvan Quan 1064837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1065837d542aSEvan Quan } AvfsDebugTable_t_NV10; 1066837d542aSEvan Quan 1067837d542aSEvan Quan typedef struct { 1068837d542aSEvan Quan uint8_t AvfsVersion; 1069837d542aSEvan Quan uint8_t Padding; 1070837d542aSEvan Quan 1071837d542aSEvan Quan uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; 1072837d542aSEvan Quan 1073837d542aSEvan Quan uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; 1074837d542aSEvan Quan uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; 1075837d542aSEvan Quan 1076837d542aSEvan Quan uint8_t OverrideTemperatures[AVFS_VOLTAGE_COUNT]; 1077837d542aSEvan Quan uint8_t OverrideVInversion[AVFS_VOLTAGE_COUNT]; 1078837d542aSEvan Quan uint8_t OverrideP2V[AVFS_VOLTAGE_COUNT]; 1079837d542aSEvan Quan uint8_t OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT]; 1080837d542aSEvan Quan 1081837d542aSEvan Quan int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1082837d542aSEvan Quan int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1083837d542aSEvan Quan int32_t VFT0_b[AVFS_VOLTAGE_COUNT]; // Q32 1084837d542aSEvan Quan 1085837d542aSEvan Quan int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1086837d542aSEvan Quan int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1087837d542aSEvan Quan int32_t VFT1_b[AVFS_VOLTAGE_COUNT]; // Q32 1088837d542aSEvan Quan 1089837d542aSEvan Quan int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16 1090837d542aSEvan Quan int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1091837d542aSEvan Quan int32_t VFT2_b[AVFS_VOLTAGE_COUNT]; // Q32 1092837d542aSEvan Quan 1093837d542aSEvan Quan int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1094837d542aSEvan Quan int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1095837d542aSEvan Quan int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT]; // Q32 1096837d542aSEvan Quan 1097837d542aSEvan Quan int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1098837d542aSEvan Quan int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1099837d542aSEvan Quan int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT]; // Q32 1100837d542aSEvan Quan 1101837d542aSEvan Quan uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT]; 1102837d542aSEvan Quan uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT]; 1103837d542aSEvan Quan uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT]; 1104837d542aSEvan Quan 1105837d542aSEvan Quan uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits 1106837d542aSEvan Quan 1107837d542aSEvan Quan 1108837d542aSEvan Quan int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24 1109837d542aSEvan Quan int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12 1110837d542aSEvan Quan int32_t P2V_b[AVFS_VOLTAGE_COUNT]; // Q32 1111837d542aSEvan Quan 1112837d542aSEvan Quan uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units 1113837d542aSEvan Quan 1114837d542aSEvan Quan uint32_t EnabledAvfsModules[2]; //NV10 - 36 AVFS modules 1115837d542aSEvan Quan 1116837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1117837d542aSEvan Quan } AvfsFuseOverride_t; 1118837d542aSEvan Quan 1119837d542aSEvan Quan typedef struct { 1120837d542aSEvan Quan 1121837d542aSEvan Quan uint8_t Gfx_ActiveHystLimit; 1122837d542aSEvan Quan uint8_t Gfx_IdleHystLimit; 1123837d542aSEvan Quan uint8_t Gfx_FPS; 1124837d542aSEvan Quan uint8_t Gfx_MinActiveFreqType; 1125837d542aSEvan Quan uint8_t Gfx_BoosterFreqType; 1126837d542aSEvan Quan uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1127837d542aSEvan Quan uint16_t Gfx_MinActiveFreq; // MHz 1128837d542aSEvan Quan uint16_t Gfx_BoosterFreq; // MHz 1129837d542aSEvan Quan uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1130837d542aSEvan Quan uint32_t Gfx_PD_Data_limit_a; // Q16 1131837d542aSEvan Quan uint32_t Gfx_PD_Data_limit_b; // Q16 1132837d542aSEvan Quan uint32_t Gfx_PD_Data_limit_c; // Q16 1133837d542aSEvan Quan uint32_t Gfx_PD_Data_error_coeff; // Q16 1134837d542aSEvan Quan uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1135837d542aSEvan Quan 1136837d542aSEvan Quan uint8_t Soc_ActiveHystLimit; 1137837d542aSEvan Quan uint8_t Soc_IdleHystLimit; 1138837d542aSEvan Quan uint8_t Soc_FPS; 1139837d542aSEvan Quan uint8_t Soc_MinActiveFreqType; 1140837d542aSEvan Quan uint8_t Soc_BoosterFreqType; 1141837d542aSEvan Quan uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1142837d542aSEvan Quan uint16_t Soc_MinActiveFreq; // MHz 1143837d542aSEvan Quan uint16_t Soc_BoosterFreq; // MHz 1144837d542aSEvan Quan uint16_t Soc_PD_Data_time_constant; // Time constant of PD controller in ms 1145837d542aSEvan Quan uint32_t Soc_PD_Data_limit_a; // Q16 1146837d542aSEvan Quan uint32_t Soc_PD_Data_limit_b; // Q16 1147837d542aSEvan Quan uint32_t Soc_PD_Data_limit_c; // Q16 1148837d542aSEvan Quan uint32_t Soc_PD_Data_error_coeff; // Q16 1149837d542aSEvan Quan uint32_t Soc_PD_Data_error_rate_coeff; // Q16 1150837d542aSEvan Quan 1151837d542aSEvan Quan uint8_t Mem_ActiveHystLimit; 1152837d542aSEvan Quan uint8_t Mem_IdleHystLimit; 1153837d542aSEvan Quan uint8_t Mem_FPS; 1154837d542aSEvan Quan uint8_t Mem_MinActiveFreqType; 1155837d542aSEvan Quan uint8_t Mem_BoosterFreqType; 1156837d542aSEvan Quan uint8_t Mem_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. 1157837d542aSEvan Quan uint16_t Mem_MinActiveFreq; // MHz 1158837d542aSEvan Quan uint16_t Mem_BoosterFreq; // MHz 1159837d542aSEvan Quan uint16_t Mem_PD_Data_time_constant; // Time constant of PD controller in ms 1160837d542aSEvan Quan uint32_t Mem_PD_Data_limit_a; // Q16 1161837d542aSEvan Quan uint32_t Mem_PD_Data_limit_b; // Q16 1162837d542aSEvan Quan uint32_t Mem_PD_Data_limit_c; // Q16 1163837d542aSEvan Quan uint32_t Mem_PD_Data_error_coeff; // Q16 1164837d542aSEvan Quan uint32_t Mem_PD_Data_error_rate_coeff; // Q16 1165837d542aSEvan Quan 1166837d542aSEvan Quan uint32_t Mem_UpThreshold_Limit; // Q16 1167837d542aSEvan Quan uint8_t Mem_UpHystLimit; 1168837d542aSEvan Quan uint8_t Mem_DownHystLimit; 1169837d542aSEvan Quan uint16_t Mem_Fps; 1170837d542aSEvan Quan 1171837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1172837d542aSEvan Quan 1173837d542aSEvan Quan } DpmActivityMonitorCoeffInt_t; 1174837d542aSEvan Quan 1175837d542aSEvan Quan 1176837d542aSEvan Quan // Workload bits 1177837d542aSEvan Quan #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1178837d542aSEvan Quan #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1179837d542aSEvan Quan #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1180837d542aSEvan Quan #define WORKLOAD_PPLIB_VIDEO_BIT 3 1181837d542aSEvan Quan #define WORKLOAD_PPLIB_VR_BIT 4 1182837d542aSEvan Quan #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1183837d542aSEvan Quan #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1184837d542aSEvan Quan #define WORKLOAD_PPLIB_COUNT 7 1185837d542aSEvan Quan 1186837d542aSEvan Quan 1187837d542aSEvan Quan // These defines are used with the following messages: 1188837d542aSEvan Quan // SMC_MSG_TransferTableDram2Smu 1189837d542aSEvan Quan // SMC_MSG_TransferTableSmu2Dram 1190837d542aSEvan Quan 1191837d542aSEvan Quan // Table transfer status 1192837d542aSEvan Quan #define TABLE_TRANSFER_OK 0x0 1193837d542aSEvan Quan #define TABLE_TRANSFER_FAILED 0xFF 1194837d542aSEvan Quan 1195837d542aSEvan Quan // Table types 1196837d542aSEvan Quan #define TABLE_PPTABLE 0 1197837d542aSEvan Quan #define TABLE_WATERMARKS 1 1198837d542aSEvan Quan #define TABLE_AVFS 2 1199837d542aSEvan Quan #define TABLE_AVFS_PSM_DEBUG 3 1200837d542aSEvan Quan #define TABLE_AVFS_FUSE_OVERRIDE 4 1201837d542aSEvan Quan #define TABLE_PMSTATUSLOG 5 1202837d542aSEvan Quan #define TABLE_SMU_METRICS 6 1203837d542aSEvan Quan #define TABLE_DRIVER_SMU_CONFIG 7 1204837d542aSEvan Quan #define TABLE_ACTIVITY_MONITOR_COEFF 8 1205837d542aSEvan Quan #define TABLE_OVERDRIVE 9 1206837d542aSEvan Quan #define TABLE_I2C_COMMANDS 10 1207837d542aSEvan Quan #define TABLE_PACE 11 1208837d542aSEvan Quan #define TABLE_COUNT 12 1209837d542aSEvan Quan 1210837d542aSEvan Quan //RLC Pace Table total number of levels 1211837d542aSEvan Quan #define RLC_PACE_TABLE_NUM_LEVELS 16 1212837d542aSEvan Quan 1213837d542aSEvan Quan typedef struct { 1214837d542aSEvan Quan float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; 1215837d542aSEvan Quan 1216837d542aSEvan Quan uint32_t MmHubPadding[8]; // SMU internal use 1217837d542aSEvan Quan } RlcPaceFlopsPerByteOverride_t; 1218837d542aSEvan Quan 1219837d542aSEvan Quan // These defines are used with the SMC_MSG_SetUclkFastSwitch message. 1220837d542aSEvan Quan #define UCLK_SWITCH_SLOW 0 1221837d542aSEvan Quan #define UCLK_SWITCH_FAST 1 1222837d542aSEvan Quan #endif 1223