Searched +full:100 +full:base +full:- +full:fx (Results 1 – 25 of 36) sorted by relevance
12
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Steen Hegelund <steen.hegelund@microchip.com>21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)22 * Adjustable tx de-emphasis (FFE)31 The SERDES6G is a high-speed SERDES interface, which can operate at34 * 100 Mbps (100BASE-FX)35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)[all …]
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - $ref: ethernet-phy.yaml#14 - Andrew Davis <afd@ti.com>17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and20 100BASE-FX Fiber protocols.23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX[all …]
3 These properties cover the base properties Micrel PHYs.7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select30 non-standard, inverted function of this configuration bit.31 Specifically, a clock reference ("rmii-ref" below) is always needed to34 - clocks, clock-names: contains clocks according to the common clock bindings.37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode47 In fiber mode, auto-negotiation is disabled and the PHY can only work in48 100base-fx (full and half duplex) modes.[all …]
1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)4 ---6 $schema: http://devicetree.org/meta-schemas/core.yaml#11 - Andrew Davis <afd@ti.com>14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It16 data over standard, twisted-pair cables or to connect to an external,17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to24 - $ref: ethernet-phy.yaml#30 ti,link-loss-low:39 ti,fiber-mode:[all …]
1 // SPDX-License-Identifier: GPL-2.0-only12 [NETIF_F_SG_BIT] = "tx-scatter-gather",13 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",14 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",15 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",17 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",18 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",20 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",21 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",22 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",[all …]
1 .. SPDX-License-Identifier: GPL-2.020 - Andrew Morton21 - Netdev mailing list <netdev@vger.kernel.org>22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>28 Since kernel 2.3.99-pre6, this driver incorporates the support for the29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.33 - 3c590 Vortex 10Mbps34 - 3c592 EISA 10Mbps Demon/Vortex35 - 3c597 EISA Fast Demon/Vortex36 - 3c595 Vortex 100baseTx[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Copyright 2010-2011 Freescale Semiconductor, Inc.11 /* Broadcom BCM54xx -- taken from linux sungem_phy */69 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm5461_config()70 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in bcm5461_config()83 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm5461_config()84 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in bcm5461_config()102 phydev->duplex = DUPLEX_HALF; in bcm54xx_parse_status()103 phydev->speed = SPEED_10; in bcm54xx_parse_status()106 phydev->duplex = DUPLEX_FULL; in bcm54xx_parse_status()[all …]
1 // SPDX-License-Identifier: GPL-2.0+13 #include "bcm-phy-lib.h"25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))43 struct bcm54xx_phy_priv *priv = phydev->priv; in bcm54xx_phy_can_wakeup()45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0; in bcm54xx_phy_can_wakeup()55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in bcm54xx_config_clock_delay()56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in bcm54xx_config_clock_delay()57 /* Disable RGMII RXC-RXD skew */ in bcm54xx_config_clock_delay()60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in bcm54xx_config_clock_delay()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only14 * struct sfp_bus - internal representation of a sfp bus36 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type43 * %PORT_TP, %PORT_FIBRE or %PORT_OTHER. If @support is non-%NULL,55 switch (id->base.connector) { in sfp_parse_port()76 if (id->base.e1000_base_t) { in sfp_parse_port()88 dev_warn(bus->sfp_dev, "SFP: unknown connector id 0x%02x\n", in sfp_parse_port()89 id->base.connector); in sfp_parse_port()111 * sfp_may_have_phy() - indicate whether the module may have a PHY120 if (id->base.e1000_base_t) in sfp_may_have_phy()[all …]
1 // SPDX-License-Identifier: GPL-2.016 #include <dt-bindings/net/ti-dp83869.h>70 /* This is the same bit mask as the BMCR so re-use the BMCR default */158 struct dp83869_private *dp83869 = phydev->priv; in dp83869_read_status()165 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) { in dp83869_read_status()166 if (phydev->link) { in dp83869_read_status()167 if (dp83869->mode == DP83869_RGMII_100_BASE) in dp83869_read_status()168 phydev->speed = SPEED_100; in dp83869_read_status()170 phydev->speed = SPEED_UNKNOWN; in dp83869_read_status()171 phydev->duplex = DUPLEX_UNKNOWN; in dp83869_read_status()[all …]
... xx PowerPC,G4 PowerPC,970 PowerPC,970FX PowerPC,POWER4 PREP MAC99 HEATHROW MAC99_U3 update-chosen ...
1 /* SPDX-License-Identifier: GPL-2.0-or-later */16 #include <sound/pcm-indirect.h>25 /* ------------------- DEFINES -------------------- */33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */41 // This is used to define hardware bit-fields (sub-registers) by combining44 // The non-concatenating (_NC) variant should be used directly only for45 // sub-registers that do not follow the <register>_<field> naming pattern.55 // Macros for manipulating values of bit-fields declared using the above macros.59 // single sub-register at a time.62 #define REG_MASK0(r) ((1U << REG_SIZE(r)) - 1U)[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used93 #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */110 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */204 /* 01010: Auto Power-Down */223 /* 10011: SerDes 100-FX Control Register */225 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */233 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */255 /* Top-MISC expansion registers */267 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>41 * init/main.c to make it non-init before enabling DEBUG_FREQ108 /* Switch CPU speed under 750FX CPU control168 udelay(100); in dfs_set_cpu_speed()210 if (++timeout > 100) in gpios_set_cpu_speed()254 * the above didn't re-enable the DEC */ in pmu_set_cpu_speed()270 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()271 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()299 switch_mmu_context(NULL, current->active_mm, NULL); in pmu_set_cpu_speed()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only40 will be called snd-adlib.55 will be called snd-ad1816a.62 CS4248 (Cirrus Logic - Crystal Semiconductors) chips.68 will be called snd-ad1848.71 tristate "Diamond Tech. DT-019x and Avance Logic ALSxxx"79 Diamond Technologies DT-019X or Avance Logic chips: ALS007,83 will be called snd-als100.96 will be called snd-azt1605.109 will be called snd-azt2316.[all …]
3 Written 2002-2004 by David Dillow <dave@thedillows.org>4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and21 number Y1-LM-2015-01.29 *) Waiting for a command response takes 8ms due to non-preemptable41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.56 /* end user-configurable values */58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).68 * There are no ill effects from too-large receive rings.89 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)[all …]
3 Written 1996-1999 by Donald Becker.43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.48 /* ARM systems perform better by disregarding the bus-master49 transfer capability of these cards. -- rmk */98 This is only in the support-all-kernels source code. */117 The Boomerang size is twice as large as the Vortex -- it has additional124 code size of a per-interface flag is not worthwhile. */137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs145 II. Board-specific settings151 The EEPROM settings for media type and forced-full-duplex are observed.[all …]
3 Written 1999-2000 by Donald Becker.19 [link no longer provides useful info -jgarzik]27 /* The user-configurable values.30 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).34 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.37 need a copy-align. */45 100mbps_hd 100Mbps half duplex.46 100mbps_fd 100Mbps full duplex.50 3 100Mbps half duplex.51 4 100Mbps full duplex.[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)9 * Low-level exception handlers and MMU support16 * This file contains the entry point for the 64-bit kernel along17 * with some early initialization code common to all 64-bit powerpc28 #include <asm/head-64.h>29 #include <asm/asm-offsets.h>42 #include <asm/ppc-opcode.h>43 #include <asm/feature-fixups.h>45 #include <asm/exception-64s.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0-only20 #include <linux/nvmem-consumer.h>35 /* svs bank 1-line software id */41 /* svs bank 2-line type */148 inode->i_private); \163 inode->i_private); \178 * enum svsb_phase - svs bank phase enumeration189 * svs bank general phase-enabled order:190 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON316 * struct svs_platform - svs platform control[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * wm5100.c -- WM5100 ALSA SoC Audio driver5 * Copyright 2011-2 Wolfson Microelectronics plc127 dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate); in wm5100_alloc_sr()128 return -EINVAL; in wm5100_alloc_sr()132 if ((wm5100->sysclk % rate) == 0) { in wm5100_alloc_sr()134 sr_free = -1; in wm5100_alloc_sr()136 if (!wm5100->sr_ref[i] && sr_free == -1) { in wm5100_alloc_sr()146 wm5100->sr_ref[i]++; in wm5100_alloc_sr()147 dev_dbg(component->dev, "SR %dHz, slot %d, ref %d\n", in wm5100_alloc_sr()[all …]
3 * Copyright 1996-1999 Thomas Bogendoerfer85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */113 PCNET32_PORT_ASEL, /* 0 Auto-select */117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */127 /* 14 MII 100BaseTx-FD */175 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)177 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)179 /* Offsets from base I/O address. */[all …]
3 Written/copyright 1999-2001 by Donald Becker.23 [link no longer provides useful info -jgarzik]62 /* Updated to recommendations in pci-skeleton v2.03. */64 /* The user-configurable values.72 static int debug = -1;76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).78 static const int multicast_filter_limit = 100;80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.101 There are no ill effects from too-large receive rings. */121 * The nic writes 32-bit values, even if the upper bytes of[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */6 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */31 #define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */32 #define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)19 #include <dt-bindings/net/mscc-phy-vsc8531.h>125 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()130 return priv->nstats; in vsc85xx_get_sset_count()135 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()141 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()142 strscpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string, in vsc85xx_get_strings()148 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()151 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()152 priv->hw_stats[i].reg); in vsc85xx_get_stat()[all …]