1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2755ccb9dSFlorian Fainelli #ifndef _LINUX_BRCMPHY_H 3755ccb9dSFlorian Fainelli #define _LINUX_BRCMPHY_H 4755ccb9dSFlorian Fainelli 54f822c62SFlorian Fainelli #include <linux/phy.h> 64f822c62SFlorian Fainelli 78bc84b79SFlorian Fainelli /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 88bc84b79SFlorian Fainelli * to configure the switch internal registers via MDIO accesses. 98bc84b79SFlorian Fainelli */ 108bc84b79SFlorian Fainelli #define BRCM_PSEUDO_PHY_ADDR 30 118bc84b79SFlorian Fainelli 126a443a0fSMatt Carlson #define PHY_ID_BCM50610 0x0143bd60 136a443a0fSMatt Carlson #define PHY_ID_BCM50610M 0x0143bd70 147a938f80SDmitry Baryshkov #define PHY_ID_BCM5241 0x0143bc30 156a443a0fSMatt Carlson #define PHY_ID_BCMAC131 0x0143bc70 16fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5481 0x0143bca0 1728dc4c8fSFlorian Fainelli #define PHY_ID_BCM5395 0x0143bcf0 18123aff2aSFlorian Fainelli #define PHY_ID_BCM53125 0x03625f20 1939bfb3c1SKurt Kanzenbach #define PHY_ID_BCM53128 0x03625e10 20b14995acSJon Mason #define PHY_ID_BCM54810 0x03625d00 21b0ed0bbfSKevin Lo #define PHY_ID_BCM54811 0x03625cc0 22fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5482 0x0143bcb0 23fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5411 0x00206070 24fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5421 0x002060e0 250fc9ae10SRafał Miłecki #define PHY_ID_BCM54210E 0x600d84a0 26fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5464 0x002060b0 27fcb26ec5SDmitry Baryshkov #define PHY_ID_BCM5461 0x002060c0 28d92ead16SXo Wang #define PHY_ID_BCM54612E 0x03625e60 293bca4cf6SAlessio Igor Bogani #define PHY_ID_BCM54616S 0x03625d10 30e4e51da6SMichael Walle #define PHY_ID_BCM54140 0xae025009 316a443a0fSMatt Carlson #define PHY_ID_BCM57780 0x03625d90 3223b83922SBhadram Varka #define PHY_ID_BCM89610 0x03625cd0 336a443a0fSMatt Carlson 3492ec804fSFlorian Fainelli #define PHY_ID_BCM72113 0x35905310 358b86850bSFlorian Fainelli #define PHY_ID_BCM72116 0x35905350 36f68d08c4SFlorian Fainelli #define PHY_ID_BCM72165 0x35905340 37430ad68fSFlorian Fainelli #define PHY_ID_BCM7250 0xae025280 388572a1b4SJustin Chen #define PHY_ID_BCM7255 0xae025120 3983ee102aSDoug Berger #define PHY_ID_BCM7260 0xae025190 4083ee102aSDoug Berger #define PHY_ID_BCM7268 0xae025090 4183ee102aSDoug Berger #define PHY_ID_BCM7271 0xae0253b0 42582d0ac3SFlorian Fainelli #define PHY_ID_BCM7278 0xae0251a0 43430ad68fSFlorian Fainelli #define PHY_ID_BCM7364 0xae025260 44b560a58cSFlorian Fainelli #define PHY_ID_BCM7366 0x600d8490 454cef191dSJaedon Shin #define PHY_ID_BCM7346 0x600d8650 464cef191dSJaedon Shin #define PHY_ID_BCM7362 0x600d84b0 47*9fa0bba0SFlorian Fainelli #define PHY_ID_BCM74165 0x359052c0 48cc4a84c3SFlorian Fainelli #define PHY_ID_BCM7425 0x600d86b0 49d068b02cSPetri Gynther #define PHY_ID_BCM7429 0x600d8730 509458ceabSFlorian Fainelli #define PHY_ID_BCM7435 0x600d8750 51b08d46b0SFlorian Fainelli #define PHY_ID_BCM74371 0xae0252e0 52b560a58cSFlorian Fainelli #define PHY_ID_BCM7439 0x600d8480 5359e33c2bSFlorian Fainelli #define PHY_ID_BCM7439_2 0xae025080 54b560a58cSFlorian Fainelli #define PHY_ID_BCM7445 0x600d8510 55218f23e8SFlorian Fainelli #define PHY_ID_BCM7712 0x35905330 56b560a58cSFlorian Fainelli 578e185d69SArun Parameswaran #define PHY_ID_BCM_CYGNUS 0xae025200 586fdecfe3SArun Parameswaran #define PHY_ID_BCM_OMEGA 0xae025100 598e185d69SArun Parameswaran 606a443a0fSMatt Carlson #define PHY_BCM_OUI_MASK 0xfffffc00 616a443a0fSMatt Carlson #define PHY_BCM_OUI_1 0x00206000 626a443a0fSMatt Carlson #define PHY_BCM_OUI_2 0x0143bc00 636a443a0fSMatt Carlson #define PHY_BCM_OUI_3 0x03625c00 6497fdaab4SFlorian Fainelli #define PHY_BCM_OUI_4 0x600d8400 65b560a58cSFlorian Fainelli #define PHY_BCM_OUI_5 0x03625e00 6611bf2bbdSFlorian Fainelli #define PHY_BCM_OUI_6 0xae025000 676a443a0fSMatt Carlson 6817d3a83aSFlorian Fainelli #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000001 6917d3a83aSFlorian Fainelli #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000002 7032aeba1fSFlorian Fainelli #define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004 7132aeba1fSFlorian Fainelli #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008 7232aeba1fSFlorian Fainelli #define PHY_BRCM_EN_MASTER_MODE 0x00000010 73ae98f40dSFlorian Fainelli #define PHY_BRCM_IDDQ_SUSPEND 0x00000020 74b14995acSJon Mason 75b560a58cSFlorian Fainelli /* Broadcom BCM7xxx specific workarounds */ 76bb7d9349SFlorian Fainelli #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 77bb7d9349SFlorian Fainelli #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 788649f13dSMatt Carlson #define PHY_BCM_FLAGS_VALID 0x80000000 79755ccb9dSFlorian Fainelli 80439d39a9SFlorian Fainelli /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 81439d39a9SFlorian Fainelli #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 82439d39a9SFlorian Fainelli #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 83439d39a9SFlorian Fainelli #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 84ab41ca34SMurali Krishna Policharla #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */ 85439d39a9SFlorian Fainelli 86439d39a9SFlorian Fainelli #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 87439d39a9SFlorian Fainelli #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 88439d39a9SFlorian Fainelli 89439d39a9SFlorian Fainelli #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 90439d39a9SFlorian Fainelli #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 91d6da08edSFlorian Fainelli #define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */ 92439d39a9SFlorian Fainelli #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 938baddaa9SFlorian Fainelli #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wake-on-LAN expansion select register */ 94439d39a9SFlorian Fainelli #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 9569e2ecccSKun Yi #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ 96439d39a9SFlorian Fainelli 97439d39a9SFlorian Fainelli #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 98439d39a9SFlorian Fainelli #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 99439d39a9SFlorian Fainelli #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 100439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 101439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 102439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 103439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 104439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 105439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 106439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 107439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 108439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 109439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 110439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 111439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 112439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 113439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 114439d39a9SFlorian Fainelli #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 115439d39a9SFlorian Fainelli 116439d39a9SFlorian Fainelli #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 117439d39a9SFlorian Fainelli #define MII_BCM54XX_SHD_WRITE 0x8000 118439d39a9SFlorian Fainelli #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 119439d39a9SFlorian Fainelli #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 120439d39a9SFlorian Fainelli 1210a32f1ffSMichael Walle #define MII_BCM54XX_RDB_ADDR 0x1e 1220a32f1ffSMichael Walle #define MII_BCM54XX_RDB_DATA 0x1f 1230a32f1ffSMichael Walle 12411ecf8c5SMichael Walle /* legacy access control via rdb/expansion register */ 12511ecf8c5SMichael Walle #define BCM54XX_RDB_REG0087 0x0087 12611ecf8c5SMichael Walle #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E) 12711ecf8c5SMichael Walle #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15) 12811ecf8c5SMichael Walle 129439d39a9SFlorian Fainelli /* 130439d39a9SFlorian Fainelli * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 131439d39a9SFlorian Fainelli */ 1325e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00 133439d39a9SFlorian Fainelli #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 134439d39a9SFlorian Fainelli #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 135ab41ca34SMurali Krishna Policharla #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000 136439d39a9SFlorian Fainelli 1375e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 1385e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 1393afd0218SRobert Hancock #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 1405e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 141439d39a9SFlorian Fainelli #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 1425e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 143439d39a9SFlorian Fainelli 1445e7bfa6cSRafał Miłecki #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 1453cf25904SXo Wang #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 146439d39a9SFlorian Fainelli 1473af20efcSFlorian Fainelli /* 1483af20efcSFlorian Fainelli * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 1493af20efcSFlorian Fainelli * BCM5482, and possibly some others. 1503af20efcSFlorian Fainelli */ 1513af20efcSFlorian Fainelli #define BCM_LED_SRC_LINKSPD1 0x0 1523af20efcSFlorian Fainelli #define BCM_LED_SRC_LINKSPD2 0x1 1533af20efcSFlorian Fainelli #define BCM_LED_SRC_XMITLED 0x2 1543af20efcSFlorian Fainelli #define BCM_LED_SRC_ACTIVITYLED 0x3 1553af20efcSFlorian Fainelli #define BCM_LED_SRC_FDXLED 0x4 1563af20efcSFlorian Fainelli #define BCM_LED_SRC_SLAVE 0x5 1573af20efcSFlorian Fainelli #define BCM_LED_SRC_INTR 0x6 1583af20efcSFlorian Fainelli #define BCM_LED_SRC_QUALITY 0x7 1593af20efcSFlorian Fainelli #define BCM_LED_SRC_RCVLED 0x8 160d06f78c4SFlorian Fainelli #define BCM_LED_SRC_WIRESPEED 0x9 1613af20efcSFlorian Fainelli #define BCM_LED_SRC_MULTICOLOR1 0xa 1623af20efcSFlorian Fainelli #define BCM_LED_SRC_OPENSHORT 0xb 1633af20efcSFlorian Fainelli #define BCM_LED_SRC_OFF 0xe /* Tied high */ 1643af20efcSFlorian Fainelli #define BCM_LED_SRC_ON 0xf /* Tied low */ 165bd5736e1SFlorian Fainelli #define BCM_LED_SRC_MASK GENMASK(3, 0) 1663af20efcSFlorian Fainelli 167450895d0SVladimir Oltean /* 168450895d0SVladimir Oltean * Broadcom Multicolor LED configurations (expansion register 4) 169450895d0SVladimir Oltean */ 170450895d0SVladimir Oltean #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04) 171450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 172450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_LINK_ACT 0x0 173450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_SPEED 0x1 174450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 175450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_FDX 0x3 176450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_OFF 0x4 177450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_ON 0x5 178450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_ALT 0x6 179450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_FLASH 0x7 180450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_LINK 0x8 181450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_ACT 0x9 182450895d0SVladimir Oltean #define BCM_LED_MULTICOLOR_PROGRAM 0xa 1833af20efcSFlorian Fainelli 1843af20efcSFlorian Fainelli /* 1853af20efcSFlorian Fainelli * BCM5482: Shadow registers 1863af20efcSFlorian Fainelli * Shadow values go into bits [14:10] of register 0x1c to select a shadow 1873af20efcSFlorian Fainelli * register to access. 1883af20efcSFlorian Fainelli */ 189d06f78c4SFlorian Fainelli 190d06f78c4SFlorian Fainelli /* 00100: Reserved control register 2 */ 191d06f78c4SFlorian Fainelli #define BCM54XX_SHD_SCR2 0x04 192d06f78c4SFlorian Fainelli #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 193d06f78c4SFlorian Fainelli #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 194d06f78c4SFlorian Fainelli #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 195d06f78c4SFlorian Fainelli #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 196d06f78c4SFlorian Fainelli 1973af20efcSFlorian Fainelli /* 00101: Spare Control Register 3 */ 1983af20efcSFlorian Fainelli #define BCM54XX_SHD_SCR3 0x05 1993af20efcSFlorian Fainelli #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 2003af20efcSFlorian Fainelli #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 2013af20efcSFlorian Fainelli #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 2025d4358edSFlorian Fainelli #define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100 2033af20efcSFlorian Fainelli 2043af20efcSFlorian Fainelli /* 01010: Auto Power-Down */ 2053af20efcSFlorian Fainelli #define BCM54XX_SHD_APD 0x0a 206a1cba561SArun Parameswaran #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 2073af20efcSFlorian Fainelli #define BCM54XX_SHD_APD_EN 0x0020 208a1cba561SArun Parameswaran #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 209a1cba561SArun Parameswaran #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 2103af20efcSFlorian Fainelli 21157fd7d59SFlorian Fainelli #define BCM54XX_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 2123af20efcSFlorian Fainelli /* LED3 / ~LINKSPD[2] selector */ 213bd5736e1SFlorian Fainelli #define BCM54XX_SHD_LEDS_SHIFT(led) (4 * (led)) 21457fd7d59SFlorian Fainelli #define BCM54XX_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 2153af20efcSFlorian Fainelli /* LED1 / ~LINKSPD[1] selector */ 21657fd7d59SFlorian Fainelli #define BCM54XX_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 217bd5736e1SFlorian Fainelli #define BCM54XX_SHD_LEDS2 0x0e /* 01110: LED Selector 2 */ 2183af20efcSFlorian Fainelli #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 2193af20efcSFlorian Fainelli #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 2203af20efcSFlorian Fainelli #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 2213af20efcSFlorian Fainelli #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 2223af20efcSFlorian Fainelli 223b9bcb953STao Ren /* 10011: SerDes 100-FX Control Register */ 224b9bcb953STao Ren #define BCM54616S_SHD_100FX_CTRL 0x13 225b9bcb953STao Ren #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */ 226b9bcb953STao Ren 227b9bcb953STao Ren /* 11111: Mode Control Register */ 228b9bcb953STao Ren #define BCM54XX_SHD_MODE 0x1f 229b9bcb953STao Ren #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ 2303afd0218SRobert Hancock #define BCM54XX_SHD_INTF_SEL_RGMII 0x02 2313afd0218SRobert Hancock #define BCM54XX_SHD_INTF_SEL_SGMII 0x04 2323afd0218SRobert Hancock #define BCM54XX_SHD_INTF_SEL_GBIC 0x06 233b9bcb953STao Ren #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ 2343af20efcSFlorian Fainelli 2353af20efcSFlorian Fainelli /* 2363af20efcSFlorian Fainelli * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 2373af20efcSFlorian Fainelli */ 2383af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_AADJ1CH0 0x001f 2393af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 2403af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 2413af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_AADJ1CH3 0x601f 2423af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 2433af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP08 0x0F08 2443af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 2453af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 2468dc84dcdSFlorian Fainelli #define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE 0x0100 2473af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP75 0x0f75 2483af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 2493af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 2503af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP96 0x0f96 2513af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP96_MYST 0x0010 2523af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP97 0x0f97 2533af20efcSFlorian Fainelli #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 2543af20efcSFlorian Fainelli 255d6da08edSFlorian Fainelli /* Top-MISC expansion registers */ 256d6da08edSFlorian Fainelli #define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06) 257d6da08edSFlorian Fainelli #define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0) 258d6da08edSFlorian Fainelli #define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2) 259d6da08edSFlorian Fainelli #define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3) 260d6da08edSFlorian Fainelli 2618baddaa9SFlorian Fainelli #define BCM54XX_TOP_MISC_LED_CTL (MII_BCM54XX_EXP_SEL_TOP + 0x0C) 2628baddaa9SFlorian Fainelli #define BCM54XX_LED4_SEL_INTR BIT(1) 2638baddaa9SFlorian Fainelli 2643af20efcSFlorian Fainelli /* 2653af20efcSFlorian Fainelli * BCM5482: Secondary SerDes registers 2663af20efcSFlorian Fainelli */ 2673af20efcSFlorian Fainelli #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 2683af20efcSFlorian Fainelli #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 2693af20efcSFlorian Fainelli #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 2703af20efcSFlorian Fainelli #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 2713af20efcSFlorian Fainelli #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 2723af20efcSFlorian Fainelli 273b14995acSJon Mason /* BCM54810 Registers */ 274b14995acSJon Mason #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90) 275b14995acSJon Mason #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0) 276b14995acSJon Mason #define BCM54810_SHD_CLK_CTL 0x3 277b14995acSJon Mason #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) 278b14995acSJon Mason 27969e2ecccSKun Yi /* BCM54612E Registers */ 28069e2ecccSKun Yi #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) 28169e2ecccSKun Yi #define BCM54612E_LED4_CLK125OUT_EN (1 << 1) 2823af20efcSFlorian Fainelli 2838baddaa9SFlorian Fainelli 2848baddaa9SFlorian Fainelli /* Wake-on-LAN registers */ 2858baddaa9SFlorian Fainelli #define BCM54XX_WOL_MAIN_CTL (MII_BCM54XX_EXP_SEL_WOL + 0x80) 2868baddaa9SFlorian Fainelli #define BCM54XX_WOL_EN BIT(0) 2878baddaa9SFlorian Fainelli #define BCM54XX_WOL_MODE_SINGLE_MPD 0 2888baddaa9SFlorian Fainelli #define BCM54XX_WOL_MODE_SINGLE_MPDSEC 1 2898baddaa9SFlorian Fainelli #define BCM54XX_WOL_MODE_DUAL 2 2908baddaa9SFlorian Fainelli #define BCM54XX_WOL_MODE_SHIFT 1 2918baddaa9SFlorian Fainelli #define BCM54XX_WOL_MODE_MASK 0x3 2928baddaa9SFlorian Fainelli #define BCM54XX_WOL_MP_MSB_FF_EN BIT(3) 2938baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_OPT_4B 0 2948baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_OPT_6B 1 2958baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_OPT_8B 2 2968baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_OPT_SHIFT 4 2978baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_OPT_MASK 0x3 2988baddaa9SFlorian Fainelli #define BCM54XX_WOL_L2_TYPE_CHK BIT(6) 2998baddaa9SFlorian Fainelli #define BCM54XX_WOL_L4IPV4UDP_CHK BIT(7) 3008baddaa9SFlorian Fainelli #define BCM54XX_WOL_L4IPV6UDP_CHK BIT(8) 3018baddaa9SFlorian Fainelli #define BCM54XX_WOL_UDPPORT_CHK BIT(9) 3028baddaa9SFlorian Fainelli #define BCM54XX_WOL_CRC_CHK BIT(10) 3038baddaa9SFlorian Fainelli #define BCM54XX_WOL_SECKEY_MODE BIT(11) 3048baddaa9SFlorian Fainelli #define BCM54XX_WOL_RST BIT(12) 3058baddaa9SFlorian Fainelli #define BCM54XX_WOL_DIR_PKT_EN BIT(13) 3068baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_DA_FF 0 3078baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_DA_MPD 1 3088baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_DA_ONLY 2 3098baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_MPD 3 3108baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_SHIFT 14 3118baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK_MODE_MASK 0x3 3128baddaa9SFlorian Fainelli 3138baddaa9SFlorian Fainelli #define BCM54XX_WOL_INNER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x81) 3148baddaa9SFlorian Fainelli #define BCM54XX_WOL_OUTER_PROTO (MII_BCM54XX_EXP_SEL_WOL + 0x82) 3158baddaa9SFlorian Fainelli #define BCM54XX_WOL_OUTER_PROTO2 (MII_BCM54XX_EXP_SEL_WOL + 0x83) 3168baddaa9SFlorian Fainelli 3178baddaa9SFlorian Fainelli #define BCM54XX_WOL_MPD_DATA1(x) (MII_BCM54XX_EXP_SEL_WOL + 0x84 + (x)) 3188baddaa9SFlorian Fainelli #define BCM54XX_WOL_MPD_DATA2(x) (MII_BCM54XX_EXP_SEL_WOL + 0x87 + (x)) 3198baddaa9SFlorian Fainelli #define BCM54XX_WOL_SEC_KEY_8B (MII_BCM54XX_EXP_SEL_WOL + 0x8A) 3208baddaa9SFlorian Fainelli #define BCM54XX_WOL_MASK(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8B + (x)) 3218baddaa9SFlorian Fainelli #define BCM54XX_SEC_KEY_STORE(x) (MII_BCM54XX_EXP_SEL_WOL + 0x8E) 3228baddaa9SFlorian Fainelli #define BCM54XX_WOL_SHARED_CNT (MII_BCM54XX_EXP_SEL_WOL + 0x92) 3238baddaa9SFlorian Fainelli 3248baddaa9SFlorian Fainelli #define BCM54XX_WOL_INT_MASK (MII_BCM54XX_EXP_SEL_WOL + 0x93) 3258baddaa9SFlorian Fainelli #define BCM54XX_WOL_PKT1 BIT(0) 3268baddaa9SFlorian Fainelli #define BCM54XX_WOL_PKT2 BIT(1) 3278baddaa9SFlorian Fainelli #define BCM54XX_WOL_DIR BIT(2) 3288baddaa9SFlorian Fainelli #define BCM54XX_WOL_ALL_INTRS (BCM54XX_WOL_PKT1 | \ 3298baddaa9SFlorian Fainelli BCM54XX_WOL_PKT2 | \ 3308baddaa9SFlorian Fainelli BCM54XX_WOL_DIR) 3318baddaa9SFlorian Fainelli 3328baddaa9SFlorian Fainelli #define BCM54XX_WOL_INT_STATUS (MII_BCM54XX_EXP_SEL_WOL + 0x94) 3338baddaa9SFlorian Fainelli 3343af20efcSFlorian Fainelli /*****************************************************************************/ 3353af20efcSFlorian Fainelli /* Fast Ethernet Transceiver definitions. */ 3363af20efcSFlorian Fainelli /*****************************************************************************/ 3373af20efcSFlorian Fainelli 3383af20efcSFlorian Fainelli #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 3393af20efcSFlorian Fainelli #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 3403af20efcSFlorian Fainelli #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 3413af20efcSFlorian Fainelli #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 3423af20efcSFlorian Fainelli #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 3433af20efcSFlorian Fainelli #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 3443af20efcSFlorian Fainelli 3453af20efcSFlorian Fainelli #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 3463af20efcSFlorian Fainelli #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 3473af20efcSFlorian Fainelli 3483af20efcSFlorian Fainelli 3493af20efcSFlorian Fainelli /*** Shadow register definitions ***/ 3503af20efcSFlorian Fainelli 3513af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 3523af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 3533af20efcSFlorian Fainelli 3543af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 3550630f64dSFlorian Fainelli #define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 /* Standby enable */ 3563af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 3573af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 3583af20efcSFlorian Fainelli 3593af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 3603af20efcSFlorian Fainelli #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 3613af20efcSFlorian Fainelli 362b8f9a029SFlorian Fainelli #define BRCM_CL45VEN_EEE_CONTROL 0x803d 363b8f9a029SFlorian Fainelli #define LPI_FEATURE_EN 0x8000 364b8f9a029SFlorian Fainelli #define LPI_FEATURE_EN_DIG1000X 0x4000 36570531479SFlorian Fainelli 366e8b6f79bSFlorian Fainelli #define BRCM_CL45VEN_EEE_LPI_CNT 0x803f 367e8b6f79bSFlorian Fainelli 3688e185d69SArun Parameswaran /* Core register definitions*/ 369820ee17bSFlorian Fainelli #define MII_BRCM_CORE_BASE12 0x12 370820ee17bSFlorian Fainelli #define MII_BRCM_CORE_BASE13 0x13 371820ee17bSFlorian Fainelli #define MII_BRCM_CORE_BASE14 0x14 3728e185d69SArun Parameswaran #define MII_BRCM_CORE_BASE1E 0x1E 3738e185d69SArun Parameswaran #define MII_BRCM_CORE_EXPB0 0xB0 3748e185d69SArun Parameswaran #define MII_BRCM_CORE_EXPB1 0xB1 3758e185d69SArun Parameswaran 37611ecf8c5SMichael Walle /* Enhanced Cable Diagnostics */ 37711ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_CTRL 0x2a0 37811ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0) 37911ecf8c5SMichael Walle 38011ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */ 38111ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */ 38211ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */ 38311ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */ 38411ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */ 38511ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */ 38611ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */ 38711ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */ 38811ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link 38911ecf8c5SMichael Walle * during test 39011ecf8c5SMichael Walle */ 39111ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair 39211ecf8c5SMichael Walle * short check 39311ecf8c5SMichael Walle */ 39411ecf8c5SMichael Walle #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */ 39511ecf8c5SMichael Walle 39611ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1 39711ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1) 39811ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0 39911ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_OK 0x1 40011ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2 40111ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */ 40211ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */ 40311ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9 40411ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0) 40511ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4) 40611ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8) 40711ecf8c5SMichael Walle #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12) 40811ecf8c5SMichael Walle #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 40911ecf8c5SMichael Walle #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 41011ecf8c5SMichael Walle #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 41111ecf8c5SMichael Walle #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 41211ecf8c5SMichael Walle 41311ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 41411ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2) 41511ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 41611ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3) 41711ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 41811ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4) 41911ecf8c5SMichael Walle #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 42011ecf8c5SMichael Walle #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5) 42111ecf8c5SMichael Walle #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff 42211ecf8c5SMichael Walle 423755ccb9dSFlorian Fainelli #endif /* _LINUX_BRCMPHY_H */ 424