| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | css_receiver_2400_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
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| H A D | css_receiver_2400_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define CSS_RECEIVER_IMG_PROC_RF_ADDR 10
34 #define CSS_RECEIVER_PRED10_VAL 10
50 …VER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1)
51 …VER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1)
52 …VER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1)
70 #define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10
90 /* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */
101 #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10
123 #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out"
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| /openbmc/linux/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ |
| H A D | mipi_backend_common_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
28 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit …
29 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit …
30 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit lega…
31 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit …
32 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit …
33 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 …
34 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 …
35 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 …
36 #define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 …
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| /openbmc/linux/tools/edid/ |
| H A D | edid.S | 18 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
36 /* Provide defaults for the timing bits */
48 ((((v1-'@')&0x1f)<<10)+(((v2-'@')&0x1f)<<5)+((v3-'@')&0x1f))
68 /* Serial number. 32 bits, little endian. */
74 /* Year of manufacture, less 1990. (1990-2245)
76 year: .byte YEAR-1990
82 Bits 6-1 Reserved, must be 0
84 1 pixel per clock, up to 8 bits per color, MSB aligned,
86 Bits 6-5 Video white and sync levels, relative to blank
87 00=+0.7/-0.3 V; 01=+0.714/-0.286 V;
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| /openbmc/u-boot/board/toradex/colibri_imx6/ |
| H A D | pf0100_otp.inc | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016, Toradex AG
11 // Time: 10:52:58
15 /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_d…
16 … sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
17 …sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.…
60 {pmic_delay, 0, 10},
67 {pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
70 {pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
71 //-----------------------------------------------------------------------------------
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | pf0100_otp.inc | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016, Toradex AG
15 /* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_d…
16 … sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
17 …sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.…
62 {pmic_delay, 0, 10},
69 {pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
72 {pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
73 //-----------------------------------------------------------------------------------
74 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
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| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pixfmt-srggb10p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
24 bytes. Each of the first 4 bytes contain the 8 high order bits
26 bits of each pixel, in the same order.
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| H A D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
46 For non-contiguous formats, no constraints are enforced by the format on the
49 All components are stored with the same number of bits per component.
57 .. flat-table:: Overview of Semi-Planar YUV Formats
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| /openbmc/linux/drivers/iio/adc/ |
| H A D | max1363.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2008-2010 Jonathan Cameron
7 * Copyright (C) 2002-2004 Stefan Eletzhofer
51 /* think about including max11600 etc - more settings */
58 /* max1363 only - though don't care on others.
79 /* max123{6-9} only */
82 /* max1363 only - merely part of channel selects or don't care for others */
87 /* max1363 strictly 0x06 - but doesn't matter */
94 * struct max1363_mode - scan mode information
122 * struct max1363_chip_info - chip specifc information
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| /openbmc/linux/arch/arc/include/asm/ |
| H A D | disasm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
32 #define BITS(word, s, e) (((word) >> (s)) & (~((-2) << ((e) - (s))))) macro
34 #define MAJOR_OPCODE(word) (BITS((word), 27, 31))
35 #define MINOR_OPCODE(word) (BITS((word), 16, 21))
36 #define FIELD_A(word) (BITS((word), 0, 5))
37 #define FIELD_B(word) ((BITS((word), 12, 14)<<3) | \
38 (BITS((word), 24, 26)))
39 #define FIELD_C(word) (BITS((word), 6, 11))
41 #define FIELD_s12(word) sign_extend(((BITS((word), 0, 5) << 6) | \
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | prcm-common.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
91 #define OMAP24XX_EN_GPT8_SHIFT 10
92 #define OMAP24XX_EN_GPT8_MASK (1 << 10)
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
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| /openbmc/qemu/tests/functional/acpi-bits/bits-tests/ |
| H A D | smilatency.py2 | 4 # SPDX-License-Identifier: BSD-3-Clause
33 import bits
49 tsc_per_sec = bits.tsc_per_sec()
51 bins = [long(tsc_per_usec * 10**i) for i in range(9)]
54 "1us < t <= 10us",
55 "10us < t <= 100us",
57 "1ms < t <= 10ms",
58 "10ms < t <= 100ms",
60 "1s < t <= 10s ",
61 "10s < t <= 100s ",
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| /openbmc/linux/drivers/crypto/hisilicon/sec2/ |
| H A D | sec_crypto.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
99 * mac_len: 0~4 bits
100 * a_key_len: 5~10 bits
101 * a_alg: 11~16 bits
106 * c_icv_len: 0~5 bits
107 * c_width: 6~8 bits
108 * c_key_len: 9~11 bits
109 * c_mode: 12~15 bits
113 /* c_alg: 0~3 bits */
118 * a_len: 0~23 bits
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| /openbmc/linux/include/uapi/linux/usb/ |
| H A D | ch11.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * From USB 2.0 spec Table 11-13, offset 7, a hub can
17 * have up to 255 ports. The most yet reported is 10.
24 /* See USB 3.1 spec Table 10-5 */
36 * See USB 3.1 spec Table 10-12
44 * See USB 2.0 spec Table 11-16
48 #define HUB_GET_TT_STATE 10
53 * See USB 3.0 spec Table 10-6
60 * See USB 2.0 spec Table 11-17
67 * See USB 2.0 spec Table 11-17
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| /openbmc/linux/drivers/media/radio/si470x/ |
| H A D | radio-si470x.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/media/radio/si470x/radio-si470x.h
12 #define DRIVER_NAME "radio-si470x"
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/v4l2-device.h>
41 #define DEVICEID_PN 0xf000 /* bits 15..12: Part Number */
42 #define DEVICEID_MFGID 0x0fff /* bits 11..00: Manufacturer ID */
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | powernow-k7.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * - We cli/sti on stepping A0 CPUs around the FID/VID transition.
13 * - We disable half multipliers if ACPI is used on A0 stepping CPUs.
38 #include "powernow-k7.h"
41 u8 signature[10];
64 } bits; member
77 /* divide by 10 to get FID. */
82 150, 225, 160, 165, 170, 180, -1, -1,
95 static unsigned int minimum_speed = -1;
107 delta = (fsbspeed > f) ? fsbspeed - f : f - fsbspeed; in check_fsb()
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| /openbmc/qemu/hw/riscv/ |
| H A D | riscv-iommu-bits.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2023 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
10 * https://github.com/riscv-non-isa/riscv-iommu
19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
23 * struct riscv_iommu_fq_record - Fault/Event Queue Record
40 * struct riscv_iommu_pq_record - PCIe Page Request record
57 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
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| /openbmc/linux/drivers/gpu/drm/exynos/ |
| H A D | regs-mixer.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Cloned from drivers/media/video/s5p-tv/regs-mixer.h
6 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
65 /* generates mask for range of bits */
67 (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
72 /* bits for MXR_STATUS */
82 /* bits for MXR_CFG */
87 #define MXR_CFG_RGB601 (0 << 10)
88 #define MXR_CFG_RGB709 (1 << 10)
110 /* bits for MXR_VIDEO_CFG */
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| /openbmc/linux/arch/x86/math-emu/ |
| H A D | README | 1 +---------------------------------------------------------------------------+
2 | wm-FPU-emu an FPU emulator for 80386 and 80486SX microprocessors. |
6 | Australia. E-mail billm@melbpc.org.au |
21 +---------------------------------------------------------------------------+
25 wm-FPU-emu is an FPU emulator for Linux. It is derived from wm-emu387
27 msdos); wm-emu387 was in turn based upon emu387 which was written by
31 My target FPU for wm-FPU-emu is that described in the Intel486
40 wm-FPU-emu does not implement all of the behaviour of the 80486 FPU,
52 --Bill Metzenthen
56 ----------------------- Internals of wm-FPU-emu -----------------------
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| /openbmc/linux/drivers/staging/media/atomisp/pci/runtime/isys/src/ |
| H A D | rx.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2010 - 2015, Intel Corporation.
26 hrt_data bits = receiver_port_reg_load(RX0_ID, in ia_css_isys_rx_enable_all_interrupts() local
30 bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) | in ia_css_isys_rx_enable_all_interrupts()
50 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); in ia_css_isys_rx_enable_all_interrupts()
104 unsigned int bits; in ia_css_isys_rx_get_irq_info() local
107 bits = ia_css_isys_rx_get_interrupt_reg(port); in ia_css_isys_rx_get_irq_info()
108 *irq_infos = ia_css_isys_rx_translate_irq_infos(bits); in ia_css_isys_rx_get_irq_info()
111 /* Translate register bits to CSS API enum mask */
112 unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits) in ia_css_isys_rx_translate_irq_infos() argument
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| /openbmc/qemu/include/standard-headers/drm/ |
| H A D | drm_fourcc.h | 38 * further describe the buffer's format - for example tiling or compression.
41 * ----------------
55 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * may preserve meaning - such as number of planes - from the fourcc code,
63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75 * - Kernel and user-space drivers: for drivers it's important that modifiers
79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92 * -----------------------
97 * upstream in-kernel or open source userspace user does not apply.
142 /* 10 bpp Red (direct relationship between channel value and brightness) */
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| /openbmc/linux/include/uapi/drm/ |
| H A D | drm_fourcc.h | 39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
143 /* 10 bpp Red (direct relationship between channel value and brightness) */
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| /openbmc/linux/drivers/net/ethernet/dec/tulip/ |
| H A D | pnic2.c | 5 Written/copyright 1994-2001 by Donald Becker.
15 /* Understanding the PNIC_II - everything is this file is based
18 * As I understand things, here are the registers and bits that
23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
24 * -----
25 * Bit 24 - SCR
26 * Bit 23 - PCS
27 * Bit 22 - TTM (Trasmit Threshold Mode)
28 * Bit 18 - Port Select
29 * Bit 13 - Start - 1, Stop - 0 Transmissions
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| /openbmc/linux/include/rdma/ |
| H A D | opa_port_info.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2014-2020 Intel Corporation. All rights reserved.
17 #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */
21 #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */
22 #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */
23 #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */
24 #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */
37 #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10
61 /* 34 -reserved */
64 /* 37-38 reserved */
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| /openbmc/linux/drivers/net/ethernet/emulex/benet/ |
| H A D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
17 * it writes the register with hi=1 and the upper bits of the physical address
20 * bits in the address. It must poll the ready bit until the command is
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
90 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
127 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
128 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
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