standard-headers/drm/drm_fourcc.h

38  * further describe the buffer's format - for example tiling or compression.
41  * ----------------
55  * vendor-namespaced, and as such the relationship between a fourcc code and a
57  * may preserve meaning - such as number of planes - from the fourcc code,
63  * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
75  * - Kernel and user-space drivers: for drivers it's important that modifiers
79  * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
92  * -----------------------
97  * upstream in-kernel or open source userspace user does not apply.
142 /* 10 bpp Red (direct relationship between channel value and brightness) */
143 #define DRM_FORMAT_R10		fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
202 #define DRM_FORMAT_XRGB2101010	fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little …
203 #define DRM_FORMAT_XBGR2101010	fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little …
204 #define DRM_FORMAT_RGBX1010102	fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little …
205 #define DRM_FORMAT_BGRX1010102	fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little …
207 #define DRM_FORMAT_ARGB2101010	fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
208 #define DRM_FORMAT_ABGR2101010	fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
209 #define DRM_FORMAT_RGBA1010102	fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
210 #define DRM_FORMAT_BGRA1010102	fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
221  * IEEE 754-2008 binary16 half-precision float
222  * [15:0] sign:exponent:mantissa 1:5:10
231  * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
234 …106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little end…
247 …VUY101010	fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier…
251  * 16-xx padding occupy lsb
253 …    fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little end…
259  * 16-xx padding occupy lsb except Y410
261 #define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
265 #define DRM_FORMAT_XVYU2101010	fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
271  * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
278 /* [63:0]   A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
280 /* [63:0]   X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0  1:1:10:10:10:1:1:10:10:10 little endian */
284  * 1-plane YUV 4:2:0
287  * These formats can only be used with a non-Linear modifier.
317 #define DRM_FORMAT_NV24		fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
318 #define DRM_FORMAT_NV42		fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
326 #define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
330  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
331  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
333 #define DRM_FORMAT_P210		fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
337  * index 0 = Y plane, [15:0] Y:x [10:6] little endian
338  * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
340 #define DRM_FORMAT_P010		fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
347 #define DRM_FORMAT_P012		fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
354 #define DRM_FORMAT_P016		fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
357  * 3 10 bit components and 2 padding bits packed into 4 bytes.
358  * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
359  * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
361 #define DRM_FORMAT_P030		fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
363 /* 3 plane non-subsampled (444) YCbCr
364  * 16 bits per component, but only 10 bits are used and 6 bits are padded
365  * index 0: Y plane, [15:0] Y:x [10:6] little endian
366  * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
367  * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
371 /* 3 plane non-subsampled (444) YCrCb
372  * 16 bits per component, but only 10 bits are used and 6 bits are padded
373  * index 0: Y plane, [15:0] Y:x [10:6] little endian
374  * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
375  * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
396 #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
397 #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
403  * Format modifiers describe, typically, a re-ordering or modification
407  * The upper 8 bits of the format modifier are a vendor-id as assigned
408  * below.  The lower 56 bits are assigned as vendor sees fit.
426 #define DRM_FORMAT_RESERVED	      ((1ULL << 56) - 1)
446  * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
448  * compatibility, in cases where a vendor-specific definition already exists and
453  * generic layouts (such as pixel re-ordering), which may have
454  * independently-developed support across multiple vendors.
457  * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
484  * which tells the driver to also take driver-internal information into account
494  * used is out-of-band information carried in an API-specific way (e.g. in a
502  * Intel X-tiling layout
505  * in row-major layout. Within the tile bytes are laid out row-major, with
506  * a platform-dependent stride. On top of that the memory can apply
507  * platform-depending swizzling of some higher address bits into bit6.
511  * cross-driver sharing. It exists since on a given platform it does uniquely
512  * identify the layout in a simple way for i915-specific userspace, which
519  * Intel Y-tiling layout
522  * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
523  * chunks column-major, with a platform-dependent height. On top of that the
524  * memory can apply platform-depending swizzling of some higher address bits
529  * cross-driver sharing. It exists since on a given platform it does uniquely
530  * identify the layout in a simple way for i915-specific userspace, which
537  * Intel Yf-tiling layout
539  * This is a tiled layout using 4Kb tiles in row-major layout.
540  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
541  * are arranged in four groups (two wide, two high) with column-major layout.
543  * out as 2x2 column-major.
555  * The main surface will be plane index 0 and must be Y/Yf-tiled,
572  * Intel color control surfaces (CCS) for Gen-12 render compression.
574  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
576  * main surface. In other words, 4 bits in CCS map to a main surface cache
578  * Y-tile widths.
583  * Intel color control surfaces (CCS) for Gen-12 media compression
585  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
587  * main surface. In other words, 4 bits in CCS map to a main surface cache
589  * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
596  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
599  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
601  * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
603  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
604  * the converted clear color of size 64 bits. The first 32 bits store the Lower
605  * Converted Clear Color value and the next 32 bits store the Higher Converted
607  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
617  * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
633 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
638  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
655  * aligned. The format of the 256 bits of clear color data matches the one used
666  * main surface. In other words, 4 bits in CCS map to a main surface cache
677  * main surface. In other words, 4 bits in CCS map to a main surface cache
679  * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
691  * be ignored. The clear color structure is 256 bits. The first 128 bits
693  * by 32 bits. The raw clear color is consumed by the 3d engine and generates
694  * the converted clear color of size 64 bits. The first 32 bits store the Lower
695  * Converted Clear Color value and the next 32 bits store the Higher Converted
697  * consumed by the DE. The last 64 bits are used to store Color Discard Enable
708  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
720  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
730  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
732  * Macroblocks are laid in a Z-shape, and each pixel data is following the
737  * - multiple of 128 pixels for the width
738  * - multiple of  32 pixels for the height
740  * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
745  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
747  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
757  * Implementation may be platform and base-format specific.
770  * Implementation may be platform and base-format specific.
783  * Implementation may be platform and base-format specific.
793  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
799  * Vivante 64x64 super-tiling layout
801  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
802  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
806  * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
811  * Vivante 4x4 tiling layout for dual-pipe
815  * compared to the non-split tiled layout.
820  * Vivante 64x64 super-tiling layout for dual-pipe
822  * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
824  * therefore halved compared to the non-split super-tiled layout.
829  * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
834  * number of status bits per entry.
835  * We reserve the top 8 bits of the Vivante modifier space for tile status
847  * as the TS bits get reinterpreted as compression tags instead of simple
853 /* Masking out the extension bits will yield the base modifier. */
880  * Bits  Param Description
881  * ----  ----- -----------------------------------------------------------------
885  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
887  *  4:4  -     Must be 1, to indicate block-linear layout.  Necessary for
889  *             DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
891  *  8:5  -     Reserved (To support 3D-surfaces with variable log2(depth) block
899  * 11:9  -     Reserved (To support 2D-array textures with variable array stride
904  *             tables of all GPUs >= NV50.  It affects the exact layout of bits
920  *               0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
921  *               1 = Gob Height 4, G80 - GT2XX Page Kind mapping
931  *               0 = Tegra K1 - Tegra Parker/TX2 Layout.
947  * 55:25 -     Reserved for future use.  Must be zero.
959  * with block-linear layouts, is remapped within drivers to the value 0xfe,
960  * which corresponds to the "generic" kind used for simple single-sample
961  * uncompressed color formats on Fermi - Volta GPUs.
978  * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1011  * vertical lines in the image. Reserve the lower 32 bits for modifier
1012  * type, and the next 24 bits for parameters. Top 8 bits are the
1021 	       ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1023 	((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) <<	\
1032  * - 64b utiles of pixels in a raster-order grid according to cpp.  It's 4x4
1035  * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1038  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
1042  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1043  *   tiles) or right-to-left (odd rows of 4k tiles).
1066  * and UV.  Some SAND-using hardware stores UV in a separate tiled
1072  * wide, but as this is a 10 bpp format that translates to 96 pixels.
1110  * the assumption is that a no-XOR tiling modifier will be created.
1118  * It provides fine-grained random access and minimizes the amount of data
1122  * represented using bits in the modifier. Not all combinations are valid,
1123  * and different devices or use-cases may support different combinations.
1130  * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1149  * Four lowest significant bits(LSBs) are reserved for block size.
1155  * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1172  * AFBC block-split
1193  * AFBC copy-block restrict
1195  * Buffers with this flag must obey the copy-block restriction. The restriction
1196  * is such that there are no copy-blocks referring across the border of 8x8
1216  * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1222  * AFBC double-buffer
1224  * Indicates that the buffer is allocated in a layout safe for front-buffer
1227 #define AFBC_FORMAT_MOD_DB      (1ULL << 10)
1232  * Indicates that the buffer includes per-superblock content hints.
1249  * Arm Fixed-Rate Compression (AFRC) modifiers
1253  * reductions in graphics and media use-cases.
1269  * ----------------   ---------------
1280  * ------   -----------------   ------------------
1289  * -----------------------------   ---------   -----------------   ------------------
1292  *          16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1293  * -----------------------------   ---------   -----------------   ------------------
1296  *          8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1297  * -----------------------------   ---------   -----------------   ------------------
1299  * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1300  * -----------------------------   ---------   -----------------   ------------------
1303  * -----------------------------   ---------   -----------------   ------------------
1322  * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1327  * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1329  * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1331  * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1345  * Indicates if the buffer uses the scanline-optimised layout
1346  * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1352  * Arm 16x16 Block U-Interleaved modifier
1371  * both in row-major order.
1385  * The underlying storage is considered to be 3 components, 8bit or 10-bit
1387  * - DRM_FORMAT_YUV420_8BIT
1388  * - DRM_FORMAT_YUV420_10BIT
1390  * The first 8 bits of the mode defines the layout, then the following 8 bits
1412  * - a body content organized in 64x32 superblocks with 4096 bytes per
1414  * - a 32 bytes per 128x64 header block
1432  * be accessible by the user-space clients, but only accessible by the
1435  * The user-space clients should expect a failure while trying to mmap
1436  * the DMA-BUF handle returned by the producer.
1461  *   - main surface
1464  *   - main surface in plane 0
1465  *   - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1468  *   - main surface in plane 0
1469  *   - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1470  *   - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1472  * For multi-plane formats the above surfaces get merged into one plane for
1475  * Bits  Parameter                Notes
1476  * ----- ------------------------ ---------------------------------------------
1492  * 55:36 -                        Reserved for future use, must be zero
1512  * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1517 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1524  *    0 - LINEAR
1525  *    1 - 256B_2D  - 2D block dimensions
1526  *    2 - 4KB_2D
1527  *    3 - 64KB_2D
1528  *    4 - 256KB_2D
1529  *    5 - 4KB_3D   - 3D block dimensions
1530  *    6 - 64KB_3D
1531  *    7 - 256KB_3D
1553  * one which is not-aligned.