1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef _css_receiver_2400_defs_h_ 179d4fa1a1SMauro Carvalho Chehab #define _css_receiver_2400_defs_h_ 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab #include "css_receiver_2400_common_defs.h" 209d4fa1a1SMauro Carvalho Chehab 219d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_DATA_WIDTH 8 229d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_RX_TRIG 4 239d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_RF_WORD 32 249d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 259d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_CSI_RF_ADDR 4 269d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_DATA_OUT 12 279d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_CHN_NO 2 289d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_DWORD_CNT 11 299d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_FORMAT_TYP 5 309d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_HRESPONSE 2 319d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_STATE_WIDTH 3 329d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_FIFO_DAT 32 339d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_CNT_VAL 2 349d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_PRED10_VAL 10 359d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_PRED12_VAL 12 369d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_CNT_WIDTH 8 379d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_WORD_CNT 16 389d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_PIXEL_LEN 6 399d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_PIXEL_CNT 5 409d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_COMP_8_BIT 8 419d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_COMP_7_BIT 7 429d4fa1a1SMauro Carvalho Chehab #define CSS_RECEIVER_COMP_6_BIT 6 439d4fa1a1SMauro Carvalho Chehab 449d4fa1a1SMauro Carvalho Chehab #define CSI_CONFIG_WIDTH 4 459d4fa1a1SMauro Carvalho Chehab 469d4fa1a1SMauro Carvalho Chehab /* division of gen_short data, ch_id and fmt_type over streaming data interface */ 479d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 489d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) 499d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) 509d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) 519d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) 529d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) 539d4fa1a1SMauro Carvalho Chehab 549d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 559d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 569d4fa1a1SMauro Carvalho Chehab 579d4fa1a1SMauro Carvalho Chehab #define hrt_css_receiver_2400_4_lane_port_offset 0x100 589d4fa1a1SMauro Carvalho Chehab #define hrt_css_receiver_2400_1_lane_port_offset 0x200 599d4fa1a1SMauro Carvalho Chehab #define hrt_css_receiver_2400_2_lane_port_offset 0x300 609d4fa1a1SMauro Carvalho Chehab #define hrt_css_receiver_2400_backend_port_offset 0x100 619d4fa1a1SMauro Carvalho Chehab 629d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 639d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 649d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 659d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 669d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 679d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 689d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 699d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 709d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 719d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 729d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 739d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 749d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 759d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 769d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 779d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 789d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 799d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 809d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 819d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 829d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 839d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 849d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 859d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 869d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 879d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 889d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 899d4fa1a1SMauro Carvalho Chehab 909d4fa1a1SMauro Carvalho Chehab /* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ 919d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 929d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 939d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 949d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 959d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 969d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 979d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 989d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 999d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 1009d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 1019d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 1029d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 1039d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 1049d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 1059d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 1069d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 1079d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 1089d4fa1a1SMauro Carvalho Chehab 1099d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" 1109d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" 1119d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" 1129d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" 1139d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" 1149d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" 1159d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" 1169d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" 1179d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" 1189d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" 1199d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" 1209d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" 1219d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" 1229d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" 1239d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" 1249d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" 1259d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" 1269d4fa1a1SMauro Carvalho Chehab 1279d4fa1a1SMauro Carvalho Chehab /* Bits for CSI2_DEVICE_READY register */ 1289d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 1299d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 1309d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 1319d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 1329d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 1339d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 1349d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 1359d4fa1a1SMauro Carvalho Chehab 1369d4fa1a1SMauro Carvalho Chehab /* Bits for CSI2_FUNC_PROG register */ 1379d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 1389d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 1399d4fa1a1SMauro Carvalho Chehab 1409d4fa1a1SMauro Carvalho Chehab /* Bits for INIT_COUNT register */ 1419d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 1429d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 1439d4fa1a1SMauro Carvalho Chehab 1449d4fa1a1SMauro Carvalho Chehab /* Bits for COUNT registers */ 1459d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 1469d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 1479d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 1489d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 1499d4fa1a1SMauro Carvalho Chehab 1509d4fa1a1SMauro Carvalho Chehab /* Bits for RAW116_18_DATAID register */ 1519d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 1529d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 1539d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 1549d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 1559d4fa1a1SMauro Carvalho Chehab 1569d4fa1a1SMauro Carvalho Chehab /* Bits for COMP_FORMAT register, this selects the compression data format */ 1579d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 1589d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 1599d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) 1609d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 1619d4fa1a1SMauro Carvalho Chehab 1629d4fa1a1SMauro Carvalho Chehab /* Bits for COMP_PREDICT register, this selects the predictor algorithm */ 1639d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 1649d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 1659d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 1669d4fa1a1SMauro Carvalho Chehab 1679d4fa1a1SMauro Carvalho Chehab /* Number of bits used for the delay registers */ 1689d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 1699d4fa1a1SMauro Carvalho Chehab 1709d4fa1a1SMauro Carvalho Chehab /* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ 1719d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 1729d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 1739d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 1749d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 1759d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 1769d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 1779d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 1789d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 1799d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 1809d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 1819d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 1829d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 1839d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 1849d4fa1a1SMauro Carvalho Chehab 1859d4fa1a1SMauro Carvalho Chehab /* BITS for backend RAW16 and RAW 18 registers */ 1869d4fa1a1SMauro Carvalho Chehab 1879d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 1889d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 1899d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 1909d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 1919d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 1929d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 1939d4fa1a1SMauro Carvalho Chehab 1949d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 1959d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 1969d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 1979d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 1989d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 1999d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 2009d4fa1a1SMauro Carvalho Chehab 2019d4fa1a1SMauro Carvalho Chehab /* These hsync and vsync values are for HSS simulation only */ 2029d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_HSYNC_VAL BIT(16) 2039d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_VSYNC_VAL BIT(17) 2049d4fa1a1SMauro Carvalho Chehab 2059d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 2069d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 2079d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) 2089d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) 2099d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) 2109d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) 2119d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) 2129d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) 2139d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) 2149d4fa1a1SMauro Carvalho Chehab 2159d4fa1a1SMauro Carvalho Chehab // SH Backend Register IDs 2169d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 2179d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 2189d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 2199d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 2209d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 2219d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 2229d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 2239d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 2249d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 2259d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 2269d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 2279d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 2289d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 2299d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 2309d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ 2319d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ 2329d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ 2339d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ 2349d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ 2359d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ 2369d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ 2379d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ 2389d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ 2399d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ 2409d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ 2419d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ 2429d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ 2439d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ 2449d4fa1a1SMauro Carvalho Chehab 2459d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 2469d4fa1a1SMauro Carvalho Chehab 2479d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 2489d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 2499d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 2509d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 2519d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 2529d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 2539d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 2549d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 2559d4fa1a1SMauro Carvalho Chehab #define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 2569d4fa1a1SMauro Carvalho Chehab 2579d4fa1a1SMauro Carvalho Chehab #endif /* _css_receiver_2400_defs_h_ */ 258