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/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
12 #define DbgPrn_PHYRW 1
17 #define DbgPrn_PHYRW 1
63 //------------------------------------------------------------
65 //------------------------------------------------------------
66 void phy_write (MAC_ENGINE *eng, int index, uint32_t data) in phy_write() argument
71 if (eng->env.is_new_mdio_reg[eng->run.mdio_idx]) { in phy_write()
73 MDIO_SET_PHY_ADDR(eng->phy.Adr) | in phy_write()
75 writel(wr_data, eng->run.mdio_base); in phy_write()
76 /* check time-out */ in phy_write()
[all …]
H A Dncsi.c1 // SPDX-License-Identifier: GPL-2.0+
17 //------------------------------------------------------------
18 int ncsi_set_error_flag(MAC_ENGINE *eng, int eflag) in ncsi_set_error_flag() argument
20 eng->flg.ncsi = eng->flg.ncsi | eflag; in ncsi_set_error_flag()
21 eng->flg.error = eng->flg.error | ERR_FLAG_NCSI_LINKFAIL; in ncsi_set_error_flag()
24 eng->flg.error, eng->flg.ncsi); in ncsi_set_error_flag()
26 return (1); in ncsi_set_error_flag()
29 //------------------------------------------------------------
30 // PHY IC(NC-SI)
31 //------------------------------------------------------------
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H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0+
25 // -------------------------------------------------------------
28 0x0000ffff, // SA:00-00-
29 0x12345678, // SA:78-56-34-12
42 //------------------------------------------------------------
44 //------------------------------------------------------------
48 printf("[MEMRd-Dat] %08x = %08x\n", addr, SWAP_4B_LEDN_MEM( readl(addr) ) ); in Read_Mem_Dat_NCSI_DD()
56 printf("[MEMRd-Des] %08x = %08x\n", addr, in Read_Mem_Des_NCSI_DD()
65 printf("[MEMRd-Dat] %08x = %08x\n", addr, in Read_Mem_Dat_DD()
74 printf("[MEMRd-Des] %08x = %08x\n", addr, in Read_Mem_Des_DD()
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H A Dcomminf.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 //---------------------------------------------------------
15 //---------------------------------------------------------
18 #define FP_IO 1
33 //---------------------------------------------------------
35 //---------------------------------------------------------
69 //---------------------------------------------------------
71 //---------------------------------------------------------
75 #define DEF_GTESTMODE 0 //[0]0: no burst mode, 1: 0xff, 2: …
76 #define DEF_GLOOP_MAX 1
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/openbmc/u-boot/arch/arm/mach-imx/
H A Dhab.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
15 #include <asm/mach-imx/hab.h>
28 ivt_hdr->magic, ivt_hdr->length, ivt_hdr->version); in ivt_header_error()
30 return 1; in ivt_header_error()
37 if (ivt_hdr->magic != IVT_HEADER_MAGIC) in verify_ivt_header()
40 if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) in verify_ivt_header()
43 if (ivt_hdr->version != IVT_HEADER_V1 && in verify_ivt_header()
44 ivt_hdr->version != IVT_HEADER_V2) in verify_ivt_header()
101 "ENG = HAB_ENG_ANY (0x00)\n",
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dg84.c37 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_bind()
39 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 8); in g84_chan_bind()
45 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_ramfc_write()
49 ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->inst, &chan->eng); in g84_chan_ramfc_write()
53 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd); in g84_chan_ramfc_write()
57 ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->inst, &chan->cache); in g84_chan_ramfc_write()
61 ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc); in g84_chan_ramfc_write()
65 ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht); in g84_chan_ramfc_write()
69 nvkm_kmap(chan->ramfc); in g84_chan_ramfc_write()
70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_chan_ramfc_write()
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H A Dnv50.c38 nvkm_ramht_remove(chan->ramht, hash); in nv50_eobj_ramht_del()
44 return nvkm_ramht_insert(chan->ramht, eobj, 0, 4, eobj->handle, engn->id << 20); in nv50_eobj_ramht_add()
50 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_stop()
52 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000); in nv50_chan_stop()
58 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_start()
60 nvkm_mask(device, 0x002600 + (chan->id * 4), 0x80000000, 0x80000000); in nv50_chan_start()
66 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_unbind()
68 nvkm_wr32(device, 0x002600 + (chan->id * 4), 0x00000000); in nv50_chan_unbind()
74 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in nv50_chan_bind()
76 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 12); in nv50_chan_bind()
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c43 struct gk104_clk_info eng[16]; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
99 P = 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
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H A Dgf100.c43 struct gf100_clk_info eng[16]; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
76 P = 1; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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H A Dgt215.c36 struct gt215_clk_info eng[nv_clk_src_max]; member
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
122 /* no post-divider on these.. in read_pll()
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/openbmc/linux/drivers/mtd/nand/
H A Decc-mxic.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
33 #define SDMA_MAIN BIT(1)
68 #define READ_NAND BIT(1)
114 static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in ext_ecc_eng_to_mxic() argument
116 return container_of(eng, struct mxic_ecc_engine, external_engine); in ext_ecc_eng_to_mxic()
119 static struct mxic_ecc_engine *pip_ecc_eng_to_mxic(struct nand_ecc_engine *eng) in pip_ecc_eng_to_mxic() argument
121 return container_of(eng, struct mxic_ecc_engine, pipelined_engine); in pip_ecc_eng_to_mxic()
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic() local
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v11_0.c74 if (!adev->in_s0ix) in gmc_v11_0_vm_fault_interrupt_state()
86 if (!adev->in_s0ix) in gmc_v11_0_vm_fault_interrupt_state()
100 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? in gmc_v11_0_process_interrupt()
102 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; in gmc_v11_0_process_interrupt()
106 addr = (u64)entry->src_data[0] << 12; in gmc_v11_0_process_interrupt()
107 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v11_0_process_interrupt()
115 if (entry->vmid_src == AMDGPU_GFXHUB(0)) in gmc_v11_0_process_interrupt()
116 RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
118 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v11_0_process_interrupt()
119 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); in gmc_v11_0_process_interrupt()
[all …]
H A Dgmc_v10_0.c79 if (!adev->in_s0ix) in gmc_v10_0_vm_fault_interrupt_state()
91 if (!adev->in_s0ix) in gmc_v10_0_vm_fault_interrupt_state()
105 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? in gmc_v10_0_process_interrupt()
107 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; in gmc_v10_0_process_interrupt()
108 bool retry_fault = !!(entry->src_data[1] & 0x80); in gmc_v10_0_process_interrupt()
109 bool write_fault = !!(entry->src_data[1] & 0x20); in gmc_v10_0_process_interrupt()
114 addr = (u64)entry->src_data[0] << 12; in gmc_v10_0_process_interrupt()
115 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v10_0_process_interrupt()
118 /* Returning 1 here also prevents sending the IV to the KFD */ in gmc_v10_0_process_interrupt()
121 if (entry->ih != &adev->irq.ih_soft && in gmc_v10_0_process_interrupt()
[all …]
H A Dgmc_v9_0.c102 [1][0] = "MP0",
111 [0][1] = "MP1",
112 [1][1] = "MP0",
113 [2][1] = "VCN",
114 [3][1] = "VCNU",
115 [4][1] = "HDP",
116 [5][1] = "XDP",
117 [6][1] = "DBGU0",
118 [7][1] = "DCE",
119 [8][1] = "DCEDWB0",
[all …]
/openbmc/linux/include/linux/
H A Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-mxic.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mtd/nand-ecc-mxic.h>
20 #include <linux/spi/spi-mem.h>
29 #define HC_CFG_TYPE_SPI_NAND 1
40 #define HC_CFG_MAN_CS_EN BIT(1)
58 #define INT_TX_NOT_FULL BIT(1)
74 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
86 #define OP_BUSW_2 1
92 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
117 #define DMAC_CFG_QE(x) (((x) + 1) << 16)
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/openbmc/linux/drivers/cpufreq/
H A Dsti-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
24 #define HW_INFO_INDEX 1
25 #define MAJOR_ID_INDEX 1
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
77 return ((socid >> VERSION_SHIFT) & 0xf) + 1; in sti_cpufreq_fetch_major()
83 struct device_node *np = dev->of_node; in sti_cpufreq_fetch_minor()
88 ret = of_property_read_u32_index(np, "st,syscfg-eng", in sti_cpufreq_fetch_minor()
154 struct device_node *np = dev->of_node; in sti_cpufreq_set_opp_info()
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/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
27 * NOTE: For engine-registers, GuC only needs the register offsets
28 * from the engine-mmio-base
76 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \
77 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \
95 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \
106 /* XE_LP Render / Compute Per-Class */
113 /* GEN8+ Render / Compute Per-Engine-Instance */
118 /* GEN8+ Media Decode/Encode Per-Engine-Instance */
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #define CPT_CTX_ILEN 1ULL
31 busy_sts |= 1ULL << i; \
34 free_sts |= 1ULL << i; \
36 (_rsp)->busy_sts_##etype = busy_sts; \
37 (_rsp)->free_sts_##etype = free_sts; \
43 struct rvu *rvu = block->rvu; in cpt_af_flt_intr_handler()
44 int blkaddr = block->addr; in cpt_af_flt_intr_handler()
46 int i, eng; in cpt_af_flt_intr_handler() local
50 dev_err_ratelimited(rvu->dev, "Received CPTAF FLT%d irq : 0x%llx", vec, reg); in cpt_af_flt_intr_handler()
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/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Dsdma.h1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
3 * Copyright(c) 2015 - 2018 Intel Corporation.
22 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
25 #define SDMA_MAP_SINGLE 1
48 #define SDMA_AHG_COPY 1
61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
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/openbmc/u-boot/cmd/
H A Dfitupd.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de
23 addr = simple_strtoul(argv[1], NULL, 16); in do_fitupd()
31 "\t- run update from FIT image at addr\n"
/openbmc/linux/Documentation/devicetree/bindings/iio/accel/
H A Dmemsensing,msa311.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MEMSensing digital 3-Axis accelerometer
10 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
13 MSA311 is a tri-axial, low-g accelerometer with I2C digital output for
15 scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements
16 with output data rates from 1Hz to 1000Hz.
18 https://cdn-shop.adafruit.com/product-files/5309/MSA311-V1.1-ENG.pdf
25 maxItems: 1
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/openbmc/qemu/hw/adc/
H A Daspeed_adc.c4 * Copyright 2017-2021 IBM Corp.
8 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
28 #define ASPEED_ADC_ENGINE_MODE_OFF (0b000 << 1)
29 #define ASPEED_ADC_ENGINE_MODE_STANDBY (0b001 << 1)
30 #define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1)
34 #define ASPEED_ADC_L_MASK ((1 << 10) - 1)
38 #define LOWER_CHANNEL_MASK ((1 << 10) - 1)
72 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in breaks_threshold()
74 int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2; in breaks_threshold()
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/openbmc/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
118 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
155 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
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/openbmc/u-boot/doc/
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
6 family of SoCs (S5PC100 [1] and S5PC110).
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
16 with -march=armv5 to allow more compilers to work. For U-Boot code this has
48 gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ);
51 gpio_direction_input(&gpio->gpio_a, 0);
54 gpio_direction_output(&gpio->gpio_a, 0, 1);
57 gpio_set_value(&gpio->gpio_a, 0, 0);
60 value = gpio_get_value(&gpio->gpio_a, 0);
65 [1] S5PC100:
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