Lines Matching +full:1 +full:- +full:eng
4 * Copyright 2017-2021 IBM Corp.
8 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
28 #define ASPEED_ADC_ENGINE_MODE_OFF (0b000 << 1)
29 #define ASPEED_ADC_ENGINE_MODE_STANDBY (0b001 << 1)
30 #define ASPEED_ADC_ENGINE_MODE_NORMAL (0b111 << 1)
34 #define ASPEED_ADC_L_MASK ((1 << 10) - 1)
38 #define LOWER_CHANNEL_MASK ((1 << 10) - 1)
72 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in breaks_threshold()
74 int a_bounds_reg = BOUNDS_CHANNEL_0 + (reg - DATA_CHANNEL_1_AND_0) * 2; in breaks_threshold()
75 int b_bounds_reg = a_bounds_reg + 1; in breaks_threshold()
76 uint32_t a_and_b = s->regs[reg]; in breaks_threshold()
77 uint32_t a_bounds = s->regs[a_bounds_reg]; in breaks_threshold()
78 uint32_t b_bounds = s->regs[b_bounds_reg]; in breaks_threshold()
93 reg < DATA_CHANNEL_1_AND_0 + s->nr_channels / 2); in read_channel_sample()
96 uint32_t value = s->regs[reg]; in read_channel_sample()
97 s->regs[reg] = update_channels(s->regs[reg]); in read_channel_sample()
100 s->regs[INTERRUPT_CONTROL] |= BIT(reg - DATA_CHANNEL_1_AND_0); in read_channel_sample()
101 qemu_irq_raise(s->irq); in read_channel_sample()
116 if (s->nr_channels <= 8) { in aspeed_adc_engine_read()
119 __func__, s->engine_id, reg - BOUNDS_CHANNEL_0); in aspeed_adc_engine_read()
124 if (s->nr_channels <= 8) { in aspeed_adc_engine_read()
127 __func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0); in aspeed_adc_engine_read()
139 value = s->regs[reg]; in aspeed_adc_engine_read()
142 if (s->nr_channels <= 8) { in aspeed_adc_engine_read()
145 __func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0); in aspeed_adc_engine_read()
151 /* Allow 16-bit reads of the data registers */ in aspeed_adc_engine_read()
159 __func__, s->engine_id, addr); in aspeed_adc_engine_read()
163 trace_aspeed_adc_engine_read(s->engine_id, addr, value); in aspeed_adc_engine_read()
174 trace_aspeed_adc_engine_write(s->engine_id, addr, value); in aspeed_adc_engine_write()
191 if (s->nr_channels <= 8) { in aspeed_adc_engine_write()
194 __func__, s->engine_id, reg - DATA_CHANNEL_1_AND_0); in aspeed_adc_engine_write()
199 if (s->nr_channels <= 8) { in aspeed_adc_engine_write()
202 __func__, s->engine_id, reg - BOUNDS_CHANNEL_0); in aspeed_adc_engine_write()
211 if (s->nr_channels <= 8) { in aspeed_adc_engine_write()
214 __func__, s->engine_id, reg - HYSTERESIS_CHANNEL_0); in aspeed_adc_engine_write()
230 __func__, s->engine_id, addr, value); in aspeed_adc_engine_write()
234 s->regs[reg] = value; in aspeed_adc_engine_write()
259 memcpy(s->regs, aspeed_adc_resets, sizeof(aspeed_adc_resets)); in aspeed_adc_engine_reset()
267 s->engine_id); in aspeed_adc_engine_realize()
269 assert(s->engine_id < 2); in aspeed_adc_engine_realize()
271 sysbus_init_irq(sbd, &s->irq); in aspeed_adc_engine_realize()
273 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_adc_engine_ops, s, name, in aspeed_adc_engine_realize()
276 sysbus_init_mmio(sbd, &s->mmio); in aspeed_adc_engine_realize()
281 .version_id = 1,
282 .minimum_version_id = 1,
290 DEFINE_PROP_UINT32("engine-id", AspeedADCEngineState, engine_id, 0),
291 DEFINE_PROP_UINT32("nr-channels", AspeedADCEngineState, nr_channels, 0),
298 dc->realize = aspeed_adc_engine_realize; in aspeed_adc_engine_class_init()
301 dc->desc = "Aspeed Analog-to-Digital Engine"; in aspeed_adc_engine_class_init()
302 dc->vmsd = &vmstate_aspeed_adc_engine; in aspeed_adc_engine_class_init()
316 uint32_t nr_channels = ASPEED_ADC_NR_CHANNELS / aac->nr_engines; in aspeed_adc_instance_init()
318 for (int i = 0; i < aac->nr_engines; i++) { in aspeed_adc_instance_init()
319 AspeedADCEngineState *engine = &s->engines[i]; in aspeed_adc_instance_init()
322 qdev_prop_set_uint32(DEVICE(engine), "engine-id", i); in aspeed_adc_instance_init()
323 qdev_prop_set_uint32(DEVICE(engine), "nr-channels", nr_channels); in aspeed_adc_instance_init()
334 for (int i = 0; i < aac->nr_engines; i++) { in aspeed_adc_set_irq()
335 uint32_t irq_status = s->engines[i].regs[INTERRUPT_CONTROL] & 0xFF; in aspeed_adc_set_irq()
339 qemu_set_irq(s->irq, !!pending); in aspeed_adc_set_irq()
349 s, NULL, aac->nr_engines); in aspeed_adc_realize()
351 sysbus_init_irq(sbd, &s->irq); in aspeed_adc_realize()
353 memory_region_init(&s->mmio, OBJECT(s), TYPE_ASPEED_ADC, in aspeed_adc_realize()
356 sysbus_init_mmio(sbd, &s->mmio); in aspeed_adc_realize()
358 for (int i = 0; i < aac->nr_engines; i++) { in aspeed_adc_realize()
359 Object *eng = OBJECT(&s->engines[i]); in aspeed_adc_realize() local
361 if (!sysbus_realize(SYS_BUS_DEVICE(eng), errp)) { in aspeed_adc_realize()
364 sysbus_connect_irq(SYS_BUS_DEVICE(eng), 0, in aspeed_adc_realize()
366 memory_region_add_subregion(&s->mmio, in aspeed_adc_realize()
368 &s->engines[i].mmio); in aspeed_adc_realize()
377 dc->realize = aspeed_adc_realize; in aspeed_adc_class_init()
378 dc->desc = "Aspeed Analog-to-Digital Converter"; in aspeed_adc_class_init()
379 aac->nr_engines = 1; in aspeed_adc_class_init()
387 dc->desc = "ASPEED 2600 ADC Controller"; in aspeed_2600_adc_class_init()
388 aac->nr_engines = 2; in aspeed_2600_adc_class_init()
396 dc->desc = "ASPEED 1030 ADC Controller"; in aspeed_1030_adc_class_init()
397 aac->nr_engines = 2; in aspeed_1030_adc_class_init()
405 dc->desc = "ASPEED 2700 ADC Controller"; in aspeed_2700_adc_class_init()
406 aac->nr_engines = 2; in aspeed_2700_adc_class_init()