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/openbmc/linux/arch/arm/mach-imx/
H A Dhardware.h21 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
35 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
41 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
43 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
44 * SAHB1 0x80000000+0x100000 -> 0xf5000000+0x100000
45 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
47 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
48 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
49 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
51 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
[all …]
/openbmc/linux/arch/xtensa/boot/dts/
H A Dvirt.dts14 memory@0 {
16 reg = <0x00000000 0x80000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
31 #clock-cells = <0>;
40 * two cells: second cell == 0: internal irq number
43 #address-cells = <0>;
53 #interrupt-cells = <0x1>;
55 bus-range = <0x0 0x3e>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53-ard.dts17 reg = <0x70000000 0x40000000>;
24 reg = <0xf4000000 0x3ff0000>;
29 reg = <0xf4000000 0x2000000>;
32 interrupts = <31 0x8>;
59 gpios = <&gpio5 10 0>;
66 gpios = <&gpio5 11 0>;
73 gpios = <&gpio5 12 0>;
80 gpios = <&gpio5 13 0>;
86 gpios = <&gpio4 0 0>;
94 pinctrl-0 = <&pinctrl_esdhc1>;
[all …]
/openbmc/u-boot/configs/
H A Dmx53ard_defconfig3 CONFIG_SYS_TEXT_BASE=0x77800000
23 CONFIG_SMC911X_BASE=0xF4000000
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dhisilicon,kirin-pcie.yaml77 reg = <0x0 0xf4000000 0x0 0x1000>,
78 <0x0 0xff3fe000 0x0 0x1000>,
79 <0x0 0xf3f20000 0x0 0x40000>,
80 <0x0 0xf5000000 0x0 0x2000>;
82 bus-range = <0x0 0xff>;
86 ranges = <0x02000000 0x0 0x00000000
87 0x0 0xf6000000
88 0x0 0x02000000>;
91 interrupts = <0 283 4>;
93 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
/openbmc/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
H A Dcache.h17 #define SH_CCR 0xff00001c /* Address of Cache Control Register */
18 #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
19 #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
20 #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
21 #define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
22 #define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
23 #define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
24 #define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
25 #define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
26 #define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dorion-nand.txt9 - cle : Address line number connected to CLE. Default is 0
23 cle = <0>;
28 reg = <0xf4000000 0x400>;
30 partition@0 {
32 reg = <0x0000000 0x100000>;
38 reg = <0x0100000 0x200000>;
43 reg = <0x0300000 0x100000>;
48 reg = <0x0400000 0x7d00000>;
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dbman-portals.txt44 ranges = <0 0xf 0xf4000000 0x200000>;
46 bman-portal@0 {
47 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
48 reg = <0x0 0x4000>, <0x100000 0x1000>;
49 interrupts = <105 2 0 0>;
52 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
53 reg = <0x4000 0x4000>, <0x101000 0x1000>;
54 interrupts = <107 2 0 0>;
/openbmc/linux/arch/arm/include/debug/
H A Dimx.S20 (((x) & 0x80000000) >> 7) | \
21 (0xf4000000 + \
22 (((x) & 0x50000000) >> 6) + \
23 (((x) & 0x0b000000) >> 4) + \
24 (((x) & 0x000fffff))))
35 str \rd, [\rx, #0x40] @ TXDATA
45 1002: ldr \rd, [\rx, #0x98] @ SR2
/openbmc/u-boot/include/configs/
H A D10m50_devboard.h29 #define CONFIG_SYS_RX_ETH_BUFFER 0
48 #define CONFIG_SYS_SDRAM_BASE 0xc8000000
49 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
51 #define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
55 #define CONFIG_SYS_MALLOC_LEN 0x20000
65 #define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
67 #define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN)
72 #define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
78 0x10000)
/openbmc/u-boot/doc/mvebu/
H A Darmada-8k-memory.txt13 0x00000000 0xEFFFFFFF DRAM
15 0xF0000000 0xF0FFFFFF AP Internal registers space
17 0xF1000000 0xF1FFFFFF Reserved.
19 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers
22 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers
25 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space.
27 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space.
29 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space.
31 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space.
33 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space.
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh4.h10 #define CCR_CACHE_STOP 0x00000808
11 #define CCR_CACHE_ENABLE 0x00000101
12 #define CCR_CACHE_ICI 0x00000800
14 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000
54 #define PMB_ADDR_ARRAY 0xf6100000
58 #define PMB_DATA_ARRAY 0xf7100000
66 #define PMB_WT 0 /* Write-through */
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan9115.yaml103 reg = <0xf4000000 0x2000000>;
/openbmc/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dcpu.h15 #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
16 #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
31 CPU_TARGET_DRAM = 0x0,
32 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
33 CPU_TARGET_ETH23 = 0x3,
34 CPU_TARGET_PCIE02 = 0x4,
35 CPU_TARGET_ETH01 = 0x7,
36 CPU_TARGET_PCIE13 = 0x8,
37 CPU_TARGET_SASRAM = 0x9,
38 CPU_TARGET_SATA01 = 0xa, /* A38X */
[all …]
/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Doca4080.dts58 size = <0 0x1000000>;
59 alignment = <0 0x1000000>;
62 size = <0 0x400000>;
63 alignment = <0 0x400000>;
66 size = <0 0x2000000>;
67 alignment = <0 0x2000000>;
72 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
76 ranges = <0x0 0xf 0xf4000000 0x200000>;
80 ranges = <0x0 0xf 0xf4200000 0x200000>;
84 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dkmcoge4.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x-kuroboxpro.dts59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
60 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
61 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>,
62 <MBUS_ID(0x01, 0x1e) 0 0xfc000000 0x1000000>;
67 reg = <0x00000000 0x8000000>;
86 reg = <MBUS_ID(0x01, 0x1e) 0 0x400>;
87 cle = <0>;
96 uImage@0 { /* 4 MB */
97 reg = <0 0x400000>;
102 reg = <0x400000 0x4000000>;
[all …]
H A Dorion5x-rd88f5182-nas.dts15 reg = <0x00000000 0x4000000>; /* 64 MB */
24 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
25 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
26 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
27 <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
32 pinctrl-0 = <&pmx_debug_led>;
35 led@0 {
38 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
49 devbus,badr-skew-ps = <0>;
58 flash@0 {
[all …]
H A Dorion5x-linkstation.dtsi55 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
56 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
57 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
67 #size-cells = <0>;
68 pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
109 flash@0 {
111 reg = <0 0x40000>;
119 header@0 {
120 reg = <0 0x30000>;
125 reg = <0x30000 0xF000>;
[all …]
H A Dorion5x-netgear-wnr854t.dts20 reg = <0x00000000 0x2000000>; /* 32 MB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
29 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
30 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x800000>;
35 pinctrl-0 = <&pmx_reset_button>;
47 pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>;
50 led@0 {
52 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
72 flash@0 {
74 reg = <0 0x800000>;
[all …]

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