Lines Matching +full:0 +full:xf4000000

15 #define MVEBU_REG_PCIE_DEVID		(MVEBU_REG_PCIE_BASE + 0x00)
16 #define MVEBU_REG_PCIE_REVID		(MVEBU_REG_PCIE_BASE + 0x08)
31 	CPU_TARGET_DRAM = 0x0,
32 	CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
33 	CPU_TARGET_ETH23 = 0x3,
34 	CPU_TARGET_PCIE02 = 0x4,
35 	CPU_TARGET_ETH01 = 0x7,
36 	CPU_TARGET_PCIE13 = 0x8,
37 	CPU_TARGET_SASRAM = 0x9,
38 	CPU_TARGET_SATA01 = 0xa, /* A38X */
39 	CPU_TARGET_NAND = 0xd,
40 	CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
44 	CPU_ATTR_SASRAM = 0x01,
45 	CPU_ATTR_DRAM_CS0 = 0x0e,
46 	CPU_ATTR_DRAM_CS1 = 0x0d,
47 	CPU_ATTR_DRAM_CS2 = 0x0b,
48 	CPU_ATTR_DRAM_CS3 = 0x07,
49 	CPU_ATTR_NANDFLASH = 0x2f,
50 	CPU_ATTR_SPIFLASH = 0x1e,
51 	CPU_ATTR_SPI0_CS0 = 0x1e,
52 	CPU_ATTR_SPI0_CS1 = 0x5e,
53 	CPU_ATTR_SPI1_CS2 = 0x9a,
54 	CPU_ATTR_BOOTROM = 0x1d,
55 	CPU_ATTR_PCIE_IO = 0xe0,
56 	CPU_ATTR_PCIE_MEM = 0xe8,
57 	CPU_ATTR_DEV_CS0 = 0x3e,
58 	CPU_ATTR_DEV_CS1 = 0x3d,
59 	CPU_ATTR_DEV_CS2 = 0x3b,
60 	CPU_ATTR_DEV_CS3 = 0x37,
71 #define MVEBU_SDRAM_SIZE_MAX	0xc0000000
78 #define MBUS_PCI_IO_BASE	0xF1100000
80 #define MBUS_SPI_BASE		0xF4000000
82 #define MBUS_BOOTROM_BASE	0xF8000000
98 	u8 pad1[0x54];
100 	u8 pad1[0x60];
102 	u32 rstoutn_mask; /* 0x60 */
103 	u32 sys_soft_rst; /* 0x64 */