Home
last modified time | relevance | path

Searched +full:0 +full:xf04 (Results 1 – 25 of 80) sorted by relevance

1234

/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2l-netcp.dtsi18 queue-range = <0 0x2000>;
19 linkram0 = <0x100000 0x4000>;
20 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
27 managed-queues = <0 0x2000>;
28 reg = <0x2a40000 0x20000>,
29 <0x2a06000 0x400>,
30 <0x2a02000 0x1000>,
31 <0x2a03000 0x1000>,
32 <0x23a80000 0x20000>,
33 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2hk-netcp.dtsi18 queue-range = <0 0x4000>;
19 linkram0 = <0x100000 0x8000>;
20 linkram1 = <0x0 0x10000>;
27 managed-queues = <0 0x2000>;
28 reg = <0x2a40000 0x20000>,
29 <0x2a06000 0x400>,
30 <0x2a02000 0x1000>,
31 <0x2a03000 0x1000>,
32 <0x23a80000 0x20000>,
33 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2e-netcp.dtsi18 queue-range = <0 0x2000>;
19 linkram0 = <0x100000 0x4000>;
20 linkram1 = <0 0x10000>;
27 managed-queues = <0 0x2000>;
28 reg = <0x2a40000 0x20000>,
29 <0x2a06000 0x400>,
30 <0x2a02000 0x1000>,
31 <0x2a03000 0x1000>,
32 <0x23a80000 0x20000>,
33 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2g-netcp.dtsi20 queue-range = <0 0x80>;
21 linkram0 = <0x4020000 0x7ff>;
28 managed-queues = <0 0x80>;
29 reg = <0x4100000 0x800>,
30 <0x4040000 0x100>,
31 <0x4080000 0x800>,
32 <0x40c0000 0x800>;
40 qpend-0 {
42 interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04
43 0 311 0xf04 0 312 0xf04 0 313 0xf04
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2l-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2hk-netcp.dtsi15 queue-range = <0 0x4000>;
16 linkram0 = <0x100000 0x8000>;
17 linkram1 = <0x0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
H A Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x4100000 0x800>,
28 <0x4040000 0x100>,
29 <0x4080000 0x800>,
30 <0x40c0000 0x800>;
38 qpend-0 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt27 external link ram entries. If the address is specified as "0"
83 0 : None, i.e interrupt on list full only
123 queue-range = <0 0x4000>;
124 linkram0 = <0x100000 0x8000>;
125 linkram1 = <0x0 0x10000>;
132 managed-queues = <0 0x2000>;
133 reg = <0x2a40000 0x20000>,
134 <0x2a06000 0x400>,
135 <0x2a02000 0x1000>,
136 <0x2a03000 0x1000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl64.dtsi28 reg = <0 0x70000000 0 0x100>;
29 interrupts = <0 2 0xf04>;
36 reg = <0 0x70100000 0 0x100>;
37 interrupts = <0 3 0xf04>;
44 reg = <0 0x70200000 0 0x100>;
45 interrupts = <0 4 0xf04>;
52 reg = <0 0x70300000 0 0x100>;
53 interrupts = <0 5 0xf04>;
62 #clock-cells = <0>;
/openbmc/linux/arch/arm/boot/dts/hisilicon/
H A Dhip01.dtsi19 #address-cells = <0>;
21 reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>;
26 #clock-cells = <0>;
36 ranges = <0 0x10000000 0x20000000>;
46 reg = <0x10001000 0x1000>;
50 interrupts = <0 32 4>;
56 reg = <0x10002000 0x1000>;
60 interrupts = <0 33 4>;
66 reg = <0x10003000 0x1000>;
70 interrupts = <0 34 4>;
[all …]
/openbmc/linux/sound/pci/hda/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pbx-a9.dts32 arm,hbi = <0x182>;
36 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0>;
58 reg = <0x1>;
65 reg = <0x1f002000 0x1000>;
83 reg = <0x1f000000 0x100>;
88 reg = <0x1f000600 0x20>;
90 interrupts = <1 13 0xf04>;
95 reg = <0x1f000620 0x20>;
[all …]
H A Darm-realview-eb-mp.dtsi46 reg = <0x1f001000 0x1000>,
47 <0x1f000100 0x100>;
56 reg = <0x10041000 0x1000>,
57 <0x10040000 0x100>;
59 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
64 reg = <0x1f002000 0x1000>;
66 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
67 <0 30 IRQ_TYPE_LEVEL_HIGH>,
68 <0 31 IRQ_TYPE_LEVEL_HIGH>;
88 reg = <0x1f000000 0x100>;
[all …]
H A Dvexpress-v2p-ca9.dts16 arm,hbi = <0x191>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 A9_0: cpu@0 {
41 reg = <0>;
69 reg = <0x60000000 0x40000000>;
77 /* Chipselect 3 is physically at 0x4c000000 */
81 reg = <0x4c000000 0x00800000>;
88 reg = <0x10020000 0x1000>;
90 interrupts = <0 44 4>;
[all …]
/openbmc/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_wdma.h10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
H A Dmdp_reg_wrot.h10 #define VIDO_CTRL 0x000
11 #define VIDO_MAIN_BUF_SIZE 0x008
12 #define VIDO_SOFT_RST 0x010
13 #define VIDO_SOFT_RST_STAT 0x014
14 #define VIDO_CROP_OFST 0x020
15 #define VIDO_TAR_SIZE 0x024
16 #define VIDO_OFST_ADDR 0x02c
17 #define VIDO_STRIDE 0x030
18 #define VIDO_OFST_ADDR_C 0x038
19 #define VIDO_STRIDE_C 0x03c
[all …]
/openbmc/linux/drivers/soc/mediatek/
H A Dmt8183-mmsys.h6 #define MT8183_DISP_OVL0_MOUT_EN 0xf00
7 #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
8 #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
9 #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
10 #define MT8183_DISP_PATH0_SEL_IN 0xf24
11 #define MT8183_DISP_DSI0_SEL_IN 0xf2c
12 #define MT8183_DISP_DPI0_SEL_IN 0xf30
13 #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
14 #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
17 #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
[all …]
H A Dmt8192-mmsys.h6 #define MT8192_MMSYS_OVL_MOUT_EN 0xf04
7 #define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
8 #define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
9 #define MT8192_DISP_OVL0_MOUT_EN 0xf1c
10 #define MT8192_DISP_RDMA0_SEL_IN 0xf2c
11 #define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
12 #define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
13 #define MT8192_DISP_AAL0_SEL_IN 0xf38
14 #define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
15 #define MT8192_DISP_DSI0_SEL_IN 0xf40
[all …]
H A Dmt8186-mmsys.h7 #define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
8 #define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
9 #define MT8186_DPI_RGB888_SDR_CON 0
14 #define MT8186_MMSYS_OVL_CON 0xF04
15 #define MT8186_MMSYS_OVL0_CON_MASK 0x3
16 #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
17 #define MT8186_OVL0_GO_BLEND BIT(0)
21 #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
22 #define MT8186_RDMA0_SOUT_SEL_MASK 0xF
23 #define MT8186_RDMA0_SOUT_TO_DSI0 (0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml67 enum: [ 0, 1, 2 ]
74 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
78 SPI interrupts are in the range [0-987]. PPI interrupts are in the
79 range [0-15].
82 bits[3:0] trigger type and level flags.
150 "^v2m@[0-9a-f]+$":
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
[all …]
/openbmc/linux/include/linux/amba/
H A Dsp810.h18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
/openbmc/linux/arch/arm/mach-highbank/
H A Dsysregs.h16 #define HB_SREG_A9_PWR_REQ 0xf00
17 #define HB_SREG_A9_BOOT_STAT 0xf04
18 #define HB_SREG_A9_BOOT_DATA 0xf08
20 #define HB_PWR_SUSPEND 0
25 #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
29 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_set_core_pwr()
38 int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0); in highbank_clear_core_pwr()
42 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); in highbank_clear_core_pwr()
71 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
/openbmc/linux/arch/arm/boot/dts/calxeda/
H A Decx-2000.dts9 /memreserve/ 0x00000000 0x0001000;
19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0>;
54 memory@0 {
57 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
63 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
67 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
70 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
71 <1 14 0xf08>,
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dspl.c16 #define AST_BOOTMODE_SPI 0
20 #define SCU_BASE 0x1e6e2000
21 #define SCU_SMP_SEC_ENTRY (SCU_BASE + 0x1bc)
22 #define SCU_WPROT2 (SCU_BASE + 0xf04)
34 uclass_get_device(UCLASS_PINCTRL, 0, &dev); in board_init_f()
74 spl_boot_list[0] = spl_boot_device(); in board_boot_order()
82 return 0; in spl_start_uboot()
108 return 0; in board_fit_config_name_match()
122 writel(0, 0x1e620064); in spl_boot_from_uart_wdt_disable()
123 writel(0, 0x1e6f20a0); in spl_boot_from_uart_wdt_disable()

1234