15f9b5b75SYongqiang Niu /* SPDX-License-Identifier: GPL-2.0-only */ 25f9b5b75SYongqiang Niu 35f9b5b75SYongqiang Niu #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H 45f9b5b75SYongqiang Niu #define __SOC_MEDIATEK_MT8186_MMSYS_H 55f9b5b75SYongqiang Niu 6b404cb45SXinlei Lee /* Values for DPI configuration in MMSYS address space */ 7b404cb45SXinlei Lee #define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400 8*e6c7e621SXinlei Lee #define MT8186_DPI_FORMAT_MASK GENMASK(1, 0) 9*e6c7e621SXinlei Lee #define MT8186_DPI_RGB888_SDR_CON 0 10*e6c7e621SXinlei Lee #define MT8186_DPI_RGB888_DDR_CON 1 11*e6c7e621SXinlei Lee #define MT8186_DPI_RGB565_SDR_CON 2 12*e6c7e621SXinlei Lee #define MT8186_DPI_RGB565_DDR_CON 3 13b404cb45SXinlei Lee 145f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL_CON 0xF04 155f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL0_CON_MASK 0x3 165f9b5b75SYongqiang Niu #define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC 175f9b5b75SYongqiang Niu #define MT8186_OVL0_GO_BLEND BIT(0) 185f9b5b75SYongqiang Niu #define MT8186_OVL0_GO_BG BIT(1) 195f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_GO_BLEND BIT(2) 205f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_GO_BG BIT(3) 215f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C 225f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_SEL_MASK 0xF 235f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_DSI0 (0) 245f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_COLOR0 (1) 255f9b5b75SYongqiang Niu #define MT8186_RDMA0_SOUT_TO_DPI0 (2) 265f9b5b75SYongqiang Niu #define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 275f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_EN_MASK 0xF 285f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) 295f9b5b75SYongqiang Niu #define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) 305f9b5b75SYongqiang Niu #define MT8186_DISP_OVL0_MOUT_EN 0xF18 315f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_EN_MASK 0xF 325f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) 335f9b5b75SYongqiang Niu #define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) 345f9b5b75SYongqiang Niu #define MT8186_DISP_DITHER0_MOUT_EN 0xF20 355f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_EN_MASK 0xF 365f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) 375f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) 385f9b5b75SYongqiang Niu #define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) 395f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA0_SEL_IN 0xF28 405f9b5b75SYongqiang Niu #define MT8186_RDMA0_SEL_IN_MASK 0xF 415f9b5b75SYongqiang Niu #define MT8186_RDMA0_FROM_OVL0 0 425f9b5b75SYongqiang Niu #define MT8186_RDMA0_FROM_OVL0_2L 2 435f9b5b75SYongqiang Niu #define MT8186_DISP_DSI0_SEL_IN 0xF30 445f9b5b75SYongqiang Niu #define MT8186_DSI0_SEL_IN_MASK 0xF 455f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_RDMA0 0 465f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_DITHER0 1 475f9b5b75SYongqiang Niu #define MT8186_DSI0_FROM_RDMA1 2 485f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA1_MOUT_EN 0xF3C 495f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_EN_MASK 0xF 505f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) 515f9b5b75SYongqiang Niu #define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) 525f9b5b75SYongqiang Niu #define MT8186_DISP_RDMA1_SEL_IN 0xF40 535f9b5b75SYongqiang Niu #define MT8186_RDMA1_SEL_IN_MASK 0xF 545f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_OVL0 0 555f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_OVL0_2L 2 565f9b5b75SYongqiang Niu #define MT8186_RDMA1_FROM_DITHER0 3 575f9b5b75SYongqiang Niu #define MT8186_DISP_DPI0_SEL_IN 0xF44 585f9b5b75SYongqiang Niu #define MT8186_DPI0_SEL_IN_MASK 0xF 595f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_RDMA1 0 605f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_DITHER0 1 615f9b5b75SYongqiang Niu #define MT8186_DPI0_FROM_RDMA0 2 625f9b5b75SYongqiang Niu 63831785f0SRex-BC Chen #define MT8186_MMSYS_SW0_RST_B 0x160 64831785f0SRex-BC Chen 655f9b5b75SYongqiang Niu static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { 665f9b5b75SYongqiang Niu { 675f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 685f9b5b75SYongqiang Niu MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, 695f9b5b75SYongqiang Niu MT8186_OVL0_MOUT_TO_RDMA0 705f9b5b75SYongqiang Niu }, 715f9b5b75SYongqiang Niu { 725f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 735f9b5b75SYongqiang Niu MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, 745f9b5b75SYongqiang Niu MT8186_RDMA0_FROM_OVL0 755f9b5b75SYongqiang Niu }, 765f9b5b75SYongqiang Niu { 775f9b5b75SYongqiang Niu DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, 785f9b5b75SYongqiang Niu MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, 795f9b5b75SYongqiang Niu MT8186_OVL0_GO_BLEND 805f9b5b75SYongqiang Niu }, 815f9b5b75SYongqiang Niu { 825f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, 835f9b5b75SYongqiang Niu MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, 845f9b5b75SYongqiang Niu MT8186_RDMA0_SOUT_TO_COLOR0 855f9b5b75SYongqiang Niu }, 865f9b5b75SYongqiang Niu { 874e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 885f9b5b75SYongqiang Niu MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, 895f9b5b75SYongqiang Niu MT8186_DITHER0_MOUT_TO_DSI0, 905f9b5b75SYongqiang Niu }, 915f9b5b75SYongqiang Niu { 924e8988c6Sjason-jh.lin DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0, 935f9b5b75SYongqiang Niu MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, 945f9b5b75SYongqiang Niu MT8186_DSI0_FROM_DITHER0 955f9b5b75SYongqiang Niu }, 965f9b5b75SYongqiang Niu { 975f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 985f9b5b75SYongqiang Niu MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, 995f9b5b75SYongqiang Niu MT8186_OVL0_2L_MOUT_TO_RDMA1 1005f9b5b75SYongqiang Niu }, 1015f9b5b75SYongqiang Niu { 1025f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 1035f9b5b75SYongqiang Niu MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, 1045f9b5b75SYongqiang Niu MT8186_RDMA1_FROM_OVL0_2L 1055f9b5b75SYongqiang Niu }, 1065f9b5b75SYongqiang Niu { 1075f9b5b75SYongqiang Niu DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, 1085f9b5b75SYongqiang Niu MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, 1095f9b5b75SYongqiang Niu MT8186_OVL0_2L_GO_BLEND 1105f9b5b75SYongqiang Niu }, 1115f9b5b75SYongqiang Niu { 1125f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 1135f9b5b75SYongqiang Niu MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, 1145f9b5b75SYongqiang Niu MT8186_RDMA1_MOUT_TO_DPI0_SEL 1155f9b5b75SYongqiang Niu }, 1165f9b5b75SYongqiang Niu { 1175f9b5b75SYongqiang Niu DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, 1185f9b5b75SYongqiang Niu MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, 1195f9b5b75SYongqiang Niu MT8186_DPI0_FROM_RDMA1 1205f9b5b75SYongqiang Niu }, 1215f9b5b75SYongqiang Niu }; 1225f9b5b75SYongqiang Niu 1235f9b5b75SYongqiang Niu #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ 124