1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * HiSilicon Ltd. HiP01 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (c) 2014 HiSilicon Ltd. 6*724ba675SRob Herring * Copyright (c) 2014 Huawei Ltd. 7*724ba675SRob Herring * 8*724ba675SRob Herring * Author: Wang Long <long.wanglong@huawei.com> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring interrupt-parent = <&gic>; 13*724ba675SRob Herring #address-cells = <1>; 14*724ba675SRob Herring #size-cells = <1>; 15*724ba675SRob Herring 16*724ba675SRob Herring gic: interrupt-controller@1e001000 { 17*724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 18*724ba675SRob Herring #interrupt-cells = <3>; 19*724ba675SRob Herring #address-cells = <0>; 20*724ba675SRob Herring interrupt-controller; 21*724ba675SRob Herring reg = <0x1a001000 0x1000>, <0x1a000100 0x1000>; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring hisi_refclk144mhz: refclk144mkhz { 25*724ba675SRob Herring compatible = "fixed-clock"; 26*724ba675SRob Herring #clock-cells = <0>; 27*724ba675SRob Herring clock-frequency = <144000000>; 28*724ba675SRob Herring clock-output-names = "hisi:refclk144khz"; 29*724ba675SRob Herring }; 30*724ba675SRob Herring 31*724ba675SRob Herring soc { 32*724ba675SRob Herring #address-cells = <1>; 33*724ba675SRob Herring #size-cells = <1>; 34*724ba675SRob Herring compatible = "simple-bus"; 35*724ba675SRob Herring interrupt-parent = <&gic>; 36*724ba675SRob Herring ranges = <0 0x10000000 0x20000000>; 37*724ba675SRob Herring 38*724ba675SRob Herring amba-bus { 39*724ba675SRob Herring #address-cells = <1>; 40*724ba675SRob Herring #size-cells = <1>; 41*724ba675SRob Herring compatible = "simple-bus"; 42*724ba675SRob Herring ranges; 43*724ba675SRob Herring 44*724ba675SRob Herring uart0: serial@10001000 { 45*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 46*724ba675SRob Herring reg = <0x10001000 0x1000>; 47*724ba675SRob Herring clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; 48*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 49*724ba675SRob Herring reg-shift = <2>; 50*724ba675SRob Herring interrupts = <0 32 4>; 51*724ba675SRob Herring status = "disabled"; 52*724ba675SRob Herring }; 53*724ba675SRob Herring 54*724ba675SRob Herring uart1: serial@10002000 { 55*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 56*724ba675SRob Herring reg = <0x10002000 0x1000>; 57*724ba675SRob Herring clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; 58*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 59*724ba675SRob Herring reg-shift = <2>; 60*724ba675SRob Herring interrupts = <0 33 4>; 61*724ba675SRob Herring status = "disabled"; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring uart2: serial@10003000 { 65*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 66*724ba675SRob Herring reg = <0x10003000 0x1000>; 67*724ba675SRob Herring clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; 68*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 69*724ba675SRob Herring reg-shift = <2>; 70*724ba675SRob Herring interrupts = <0 34 4>; 71*724ba675SRob Herring status = "disabled"; 72*724ba675SRob Herring }; 73*724ba675SRob Herring 74*724ba675SRob Herring uart3: serial@10006000 { 75*724ba675SRob Herring compatible = "snps,dw-apb-uart"; 76*724ba675SRob Herring reg = <0x10006000 0x1000>; 77*724ba675SRob Herring clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; 78*724ba675SRob Herring clock-names = "baudclk", "apb_pclk"; 79*724ba675SRob Herring reg-shift = <2>; 80*724ba675SRob Herring interrupts = <0 4 4>; 81*724ba675SRob Herring status = "disabled"; 82*724ba675SRob Herring }; 83*724ba675SRob Herring }; 84*724ba675SRob Herring 85*724ba675SRob Herring system-controller@10000000 { 86*724ba675SRob Herring compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; 87*724ba675SRob Herring reg = <0x10000000 0x1000>; 88*724ba675SRob Herring reboot-offset = <0x4>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring global_timer@a000200 { 92*724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 93*724ba675SRob Herring reg = <0x0a000200 0x100>; 94*724ba675SRob Herring interrupts = <1 11 0xf04>; 95*724ba675SRob Herring clocks = <&hisi_refclk144mhz>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring local_timer@a000600 { 99*724ba675SRob Herring compatible = "arm,cortex-a9-twd-timer"; 100*724ba675SRob Herring reg = <0x0a000600 0x100>; 101*724ba675SRob Herring interrupts = <1 13 0xf04>; 102*724ba675SRob Herring clocks = <&hisi_refclk144mhz>; 103*724ba675SRob Herring }; 104*724ba675SRob Herring }; 105*724ba675SRob Herring}; 106