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/openbmc/linux/sound/soc/codecs/
H A Dwm2000.h9 #define WM2000_REG_SYS_START 0x8000
10 #define WM2000_REG_ANC_GAIN_CTRL 0x8fa2
11 #define WM2000_REG_MSE_TH2 0x8fdf
12 #define WM2000_REG_MSE_TH1 0x8fe0
13 #define WM2000_REG_SPEECH_CLARITY 0x8fef
14 #define WM2000_REG_SYS_WATCHDOG 0x8ff6
15 #define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7
16 #define WM2000_REG_ANA_VMID_PU_TIME 0x8ff8
17 #define WM2000_REG_CAT_FLTR_INDX 0x8ff9
18 #define WM2000_REG_CAT_GAIN_0 0x8ffa
[all …]
/openbmc/linux/drivers/dma/ti/
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-j721s2.c63 PSIL_PDMA_MCASP(0x4400),
64 PSIL_PDMA_MCASP(0x4401),
65 PSIL_PDMA_MCASP(0x4402),
66 PSIL_PDMA_MCASP(0x4403),
67 PSIL_PDMA_MCASP(0x4404),
69 PSIL_PDMA_XY_PKT(0x4600),
70 PSIL_PDMA_XY_PKT(0x4601),
71 PSIL_PDMA_XY_PKT(0x4602),
72 PSIL_PDMA_XY_PKT(0x4603),
73 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
H A Dk3-psil-j784s4.c71 PSIL_PDMA_MCASP(0x4400),
72 PSIL_PDMA_MCASP(0x4401),
73 PSIL_PDMA_MCASP(0x4402),
74 PSIL_PDMA_MCASP(0x4403),
75 PSIL_PDMA_MCASP(0x4404),
77 PSIL_PDMA_XY_PKT(0x4600),
78 PSIL_PDMA_XY_PKT(0x4601),
79 PSIL_PDMA_XY_PKT(0x4602),
80 PSIL_PDMA_XY_PKT(0x4603),
81 PSIL_PDMA_XY_PKT(0x4604),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dserdes.h17 #define MV88E6352_ADDR_SERDES 0x0f
18 #define MV88E6352_SERDES_PAGE_FIBER 0x01
19 #define MV88E6352_SERDES_IRQ 0x0b
20 #define MV88E6352_SERDES_INT_ENABLE 0x12
30 #define MV88E6352_SERDES_INT_STATUS 0x13
32 #define MV88E6352_SERDES_SPEC_CTRL2 0x1a
33 #define MV88E6352_SERDES_OUT_AMP_MASK 0x0007
35 #define MV88E6341_PORT5_LANE 0x15
37 #define MV88E6390_PORT9_LANE0 0x09
38 #define MV88E6390_PORT9_LANE1 0x12
[all …]
/openbmc/linux/include/linux/mtd/
H A Donenand_regs.h20 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
21 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
22 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
27 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
28 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
29 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
30 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
31 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
32 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
33 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Donenand_regs.h23 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
24 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
25 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
30 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
31 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
32 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
33 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
34 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
35 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
36 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-devices-platform-stratix10-rsu3 What: /sys/devices/platform/stratix10-rsu.0/current_image
10 What: /sys/devices/platform/stratix10-rsu.0/fail_image
17 What: /sys/devices/platform/stratix10-rsu.0/state
26 b[15:0]
27 Currently used only when major error is 0xF006
34 0xF001 bitstream error
35 0xF002 hardware access failure
36 0xF003 bitstream corruption
37 0xF004 internal error
38 0xF005 device error
[all …]
/openbmc/linux/drivers/tty/vt/
H A Ddefkeymap.c_shipped10 0xf200, 0xf01b, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036,
11 0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf07f, 0xf009,
12 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69,
13 0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf201, 0xf702, 0xfb61, 0xfb73,
14 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf03b,
15 0xf027, 0xf060, 0xf700, 0xf05c, 0xfb7a, 0xfb78, 0xfb63, 0xfb76,
16 0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f, 0xf700, 0xf30c,
17 0xf703, 0xf020, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,
18 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf209, 0xf307,
19 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-cards.c24 .demod = { 0x43, I2C_CLIENT_END },
25 .tv = { 0x61, 0x60, I2C_CLIENT_END },
30 * an NXP TDA8295 at 0x42 (N.B. it can possibly be at 0x4b or 0x4c too).
34 .demod = { 0x42, 0x43, I2C_CLIENT_END },
35 .tv = { 0x61, 0x60, I2C_CLIENT_END },
40 must be added under vendor 0x4444 (Conexant) as subsystem IDs.
58 { CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 },
76 .chip_config = 0x003,
77 .refresh = 0x30c,
78 .timing1 = 0x44220e82,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dti,k3-am654-cpsw-nuss.yaml19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
113 const: 0
169 "^mdio@[0-9a-f]+$":
176 "^cpts@[0-9a-f]+":
252 reg = <0x0 0x46000000 0x0 0x200000>;
254 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
260 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
[all …]
/openbmc/qemu/include/hw/ppc/
H A Dspapr_nested.h7 #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */
8 #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */
9 #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */
10 #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */
11 #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */
12 #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */
13 #define GSB_PROCESS_TBL 0x0006 /* Process Table */
14 /* RESERVED 0x0007 - 0x0BFF */
15 #define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */
16 #define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */
[all …]
/openbmc/linux/drivers/net/phy/
H A Dmarvell-88x2222.c22 #define MV_PCS_CONFIG 0xF002
23 #define MV_PCS_HOST_XAUI 0x73
24 #define MV_PCS_LINE_10GBR (0x71 << 8)
25 #define MV_PCS_LINE_1GBX_AN (0x7B << 8)
26 #define MV_PCS_LINE_SGMII_AN (0x7F << 8)
29 #define MV_PORT_RST 0xF003
35 #define MV_RX_SIGNAL_DETECT 0x000A
36 #define MV_RX_SIGNAL_DETECT_GLOBAL BIT(0)
39 #define MV_1GBX_CTRL (0x2000 + MII_BMCR)
42 #define MV_1GBX_STAT (0x2000 + MII_BMSR)
[all …]
/openbmc/u-boot/drivers/video/
H A Dformike.c12 #define TAG_READ 0x80
13 #define TAG_WRITE 0x00
15 #define TAG_DATA 0x40
16 #define TAG_COMMAND 0x00
18 #define TAG_ADDR_H 0x20
19 #define TAG_ADDR_L 0x00
28 buf[0] = tag; in spi_write_tag_val()
30 buf[0] = val; in spi_write_tag_val()
52 (addr & 0xff00) >> 8); in spi_write_com()
54 (addr & 0x00ff) >> 0); in spi_write_com()
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040 0x4>;
26 reg = <0x0 0x40f04200 0x0 0x10>;
29 pinctrl-single,function-mask = <0x00000101>;
35 reg = <0x0 0x40f04280 0x0 0x8>;
38 pinctrl-single,function-mask = <0x00000003>;
43 reg = <0x00 0x40a00000 0x00 0x100>;
53 reg = <0x00 0x41c00000 0x00 0x80000>;
54 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x43000014 0x00 0x4>;
46 reg = <0x00 0x43600000 0x00 0x10000>,
47 <0x00 0x44880000 0x00 0x20000>,
48 <0x00 0x44860000 0x00 0x20000>;
59 reg = <0x00 0x41c00000 0x00 0x100000>;
60 ranges = <0x00 0x00 0x41c00000 0x100000>;
67 /* Proxy 0 addressing */
68 reg = <0x00 0x4301c000 0x00 0x034>;
71 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x40410000 0x00 0x400>;
57 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
66 reg = <0x00 0x40420000 0x00 0x400>;
79 reg = <0x00 0x40430000 0x00 0x400>;
83 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
92 reg = <0x00 0x40440000 0x00 0x400>;
105 reg = <0x00 0x40450000 0x00 0x400>;
109 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi20 reg = <0x00 0x44083000 0x00 0x1000>;
44 reg = <0x00 0x43000014 0x00 0x4>;
51 reg = <0x00 0x43600000 0x00 0x10000>,
52 <0x00 0x44880000 0x00 0x20000>,
53 <0x00 0x44860000 0x00 0x20000>;
64 reg = <0x00 0x41c00000 0x00 0x100000>;
65 ranges = <0x00 0x00 0x41c00000 0x100000>;
72 /* Proxy 0 addressing */
73 reg = <0x00 0x4301c000 0x00 0x034>;
76 pinctrl-single,function-mask = <0xffffffff>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
39 reg = <0x0 0x40f00000 0x0 0x20000>;
42 ranges = <0x0 0x0 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x0 0x43000014 0x0 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
68 reg = <0x00 0x40f04200 0x00 0x28>;
71 pinctrl-single,function-mask = <0x0000000f>;
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dfpu.c22 #define FPSCR_RCHG 0x00000000
46 asm volatile ("sts.l fpul, @-%0\n\t" in save_fpu()
47 "sts.l fpscr, @-%0\n\t" in save_fpu()
50 "fmov.s fr15, @-%0\n\t" in save_fpu()
51 "fmov.s fr14, @-%0\n\t" in save_fpu()
52 "fmov.s fr13, @-%0\n\t" in save_fpu()
53 "fmov.s fr12, @-%0\n\t" in save_fpu()
54 "fmov.s fr11, @-%0\n\t" in save_fpu()
55 "fmov.s fr10, @-%0\n\t" in save_fpu()
56 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dhvcall.h6 #define HVSC .long 0x44000022
8 #define H_SUCCESS 0
153 #define H_VASI_INVALID 0
173 #define H_REMOVE 0x04
174 #define H_ENTER 0x08
175 #define H_READ 0x0c
176 #define H_CLEAR_MOD 0x10
177 #define H_CLEAR_REF 0x14
178 #define H_PROTECT 0x18
179 #define H_GET_TCE 0x1c
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh2a/
H A Dfpu.c21 #define FPSCR_RCHG 0x00000000
32 asm volatile("sts.l fpul, @-%0\n\t" in save_fpu()
33 "sts.l fpscr, @-%0\n\t" in save_fpu()
34 "fmov.s fr15, @-%0\n\t" in save_fpu()
35 "fmov.s fr14, @-%0\n\t" in save_fpu()
36 "fmov.s fr13, @-%0\n\t" in save_fpu()
37 "fmov.s fr12, @-%0\n\t" in save_fpu()
38 "fmov.s fr11, @-%0\n\t" in save_fpu()
39 "fmov.s fr10, @-%0\n\t" in save_fpu()
40 "fmov.s fr9, @-%0\n\t" in save_fpu()
[all …]
/openbmc/qemu/target/sh4/
H A Dtranslate.c56 #define UNALIGN(C) 0
97 for (i = 0; i < 24; i++) { in sh4_translate_init()
153 for (i = 0; i < 32; i++) in sh4_translate_init()
164 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
166 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
168 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
170 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
171 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
176 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
179 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
[all …]

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