16b8a0537SNicholas Piggin #ifndef HW_SPAPR_NESTED_H 26b8a0537SNicholas Piggin #define HW_SPAPR_NESTED_H 36b8a0537SNicholas Piggin 46b8a0537SNicholas Piggin #include "target/ppc/cpu.h" 56b8a0537SNicholas Piggin 64a575f9aSHarsh Prateek Bora /* Guest State Buffer Element IDs */ 74a575f9aSHarsh Prateek Bora #define GSB_HV_VCPU_IGNORED_ID 0x0000 /* An element whose value is ignored */ 84a575f9aSHarsh Prateek Bora #define GSB_HV_VCPU_STATE_SIZE 0x0001 /* HV internal format VCPU state size */ 94a575f9aSHarsh Prateek Bora #define GSB_VCPU_OUT_BUF_MIN_SZ 0x0002 /* Min size of the Run VCPU o/p buffer */ 104a575f9aSHarsh Prateek Bora #define GSB_VCPU_LPVR 0x0003 /* Logical PVR */ 114a575f9aSHarsh Prateek Bora #define GSB_TB_OFFSET 0x0004 /* Timebase Offset */ 124a575f9aSHarsh Prateek Bora #define GSB_PART_SCOPED_PAGETBL 0x0005 /* Partition Scoped Page Table */ 134a575f9aSHarsh Prateek Bora #define GSB_PROCESS_TBL 0x0006 /* Process Table */ 144a575f9aSHarsh Prateek Bora /* RESERVED 0x0007 - 0x0BFF */ 154a575f9aSHarsh Prateek Bora #define GSB_VCPU_IN_BUFFER 0x0C00 /* Run VCPU Input Buffer */ 164a575f9aSHarsh Prateek Bora #define GSB_VCPU_OUT_BUFFER 0x0C01 /* Run VCPU Out Buffer */ 174a575f9aSHarsh Prateek Bora #define GSB_VCPU_VPA 0x0C02 /* HRA to Guest VCPU VPA */ 184a575f9aSHarsh Prateek Bora /* RESERVED 0x0C03 - 0x0FFF */ 194a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR0 0x1000 204a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR1 0x1001 214a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR2 0x1002 224a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR3 0x1003 234a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR4 0x1004 244a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR5 0x1005 254a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR6 0x1006 264a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR7 0x1007 274a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR8 0x1008 284a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR9 0x1009 294a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR10 0x100A 304a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR11 0x100B 314a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR12 0x100C 324a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR13 0x100D 334a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR14 0x100E 344a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR15 0x100F 354a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR16 0x1010 364a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR17 0x1011 374a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR18 0x1012 384a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR19 0x1013 394a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR20 0x1014 404a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR21 0x1015 414a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR22 0x1016 424a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR23 0x1017 434a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR24 0x1018 444a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR25 0x1019 454a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR26 0x101A 464a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR27 0x101B 474a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR28 0x101C 484a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR29 0x101D 494a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR30 0x101E 504a575f9aSHarsh Prateek Bora #define GSB_VCPU_GPR31 0x101F 514a575f9aSHarsh Prateek Bora #define GSB_VCPU_HDEC_EXPIRY_TB 0x1020 524a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_NIA 0x1021 534a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MSR 0x1022 544a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_LR 0x1023 554a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_XER 0x1024 564a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_CTR 0x1025 574a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_CFAR 0x1026 584a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SRR0 0x1027 594a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SRR1 0x1028 604a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DAR 0x1029 614a575f9aSHarsh Prateek Bora #define GSB_VCPU_DEC_EXPIRE_TB 0x102A 624a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VTB 0x102B 634a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_LPCR 0x102C 644a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HFSCR 0x102D 654a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_FSCR 0x102E 664a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_FPSCR 0x102F 674a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DAWR0 0x1030 684a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DAWR1 0x1031 694a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_CIABR 0x1032 704a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PURR 0x1033 714a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SPURR 0x1034 724a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_IC 0x1035 734a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SPRG0 0x1036 744a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SPRG1 0x1037 754a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SPRG2 0x1038 764a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SPRG3 0x1039 774a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PPR 0x103A 784a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MMCR0 0x103B 794a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MMCR1 0x103C 804a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MMCR2 0x103D 814a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MMCR3 0x103E 824a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_MMCRA 0x103F 834a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SIER 0x1040 844a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SIER2 0x1041 854a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SIER3 0x1042 864a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_BESCR 0x1043 874a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_EBBHR 0x1044 884a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_EBBRR 0x1045 894a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_AMR 0x1046 904a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_IAMR 0x1047 914a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_AMOR 0x1048 924a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_UAMOR 0x1049 934a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SDAR 0x104A 944a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_SIAR 0x104B 954a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DSCR 0x104C 964a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_TAR 0x104D 974a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DEXCR 0x104E 984a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HDEXCR 0x104F 994a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HASHKEYR 0x1050 1004a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HASHPKEYR 0x1051 1014a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_CTRL 0x1052 1024a575f9aSHarsh Prateek Bora /* RESERVED 0x1053 - 0x1FFF */ 1034a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_CR 0x2000 1044a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PIDR 0x2001 1054a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DSISR 0x2002 1064a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSCR 0x2003 1074a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VRSAVE 0x2004 1084a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DAWRX0 0x2005 1094a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_DAWRX1 0x2006 1104a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC1 0x2007 1114a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC2 0x2008 1124a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC3 0x2009 1134a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC4 0x200A 1144a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC5 0x200B 1154a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PMC6 0x200C 1164a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_WORT 0x200D 1174a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_PSPB 0x200E 1184a575f9aSHarsh Prateek Bora /* RESERVED 0x200F - 0x2FFF */ 1194a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR0 0x3000 1204a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR1 0x3001 1214a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR2 0x3002 1224a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR3 0x3003 1234a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR4 0x3004 1244a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR5 0x3005 1254a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR6 0x3006 1264a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR7 0x3007 1274a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR8 0x3008 1284a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR9 0x3009 1294a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR10 0x300A 1304a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR11 0x300B 1314a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR12 0x300C 1324a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR13 0x300D 1334a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR14 0x300E 1344a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR15 0x300F 1354a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR16 0x3010 1364a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR17 0x3011 1374a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR18 0x3012 1384a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR19 0x3013 1394a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR20 0x3014 1404a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR21 0x3015 1414a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR22 0x3016 1424a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR23 0x3017 1434a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR24 0x3018 1444a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR25 0x3019 1454a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR26 0x301A 1464a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR27 0x301B 1474a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR28 0x301C 1484a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR29 0x301D 1494a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR30 0x301E 1504a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR31 0x301F 1514a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR32 0x3020 1524a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR33 0x3021 1534a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR34 0x3022 1544a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR35 0x3023 1554a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR36 0x3024 1564a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR37 0x3025 1574a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR38 0x3026 1584a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR39 0x3027 1594a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR40 0x3028 1604a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR41 0x3029 1614a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR42 0x302A 1624a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR43 0x302B 1634a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR44 0x302C 1644a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR45 0x302D 1654a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR46 0x302E 1664a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR47 0x302F 1674a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR48 0x3030 1684a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR49 0x3031 1694a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR50 0x3032 1704a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR51 0x3033 1714a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR52 0x3034 1724a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR53 0x3035 1734a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR54 0x3036 1744a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR55 0x3037 1754a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR56 0x3038 1764a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR57 0x3039 1774a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR58 0x303A 1784a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR59 0x303B 1794a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR60 0x303C 1804a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR61 0x303D 1814a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR62 0x303E 1824a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_VSR63 0x303F 1834a575f9aSHarsh Prateek Bora /* RESERVED 0x3040 - 0xEFFF */ 1844a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HDAR 0xF000 1854a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HDSISR 0xF001 1864a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_HEIR 0xF002 1874a575f9aSHarsh Prateek Bora #define GSB_VCPU_SPR_ASDR 0xF003 1884a575f9aSHarsh Prateek Bora /* End of list of Guest State Buffer Element IDs */ 1894a575f9aSHarsh Prateek Bora #define GSB_LAST GSB_VCPU_SPR_ASDR 1904a575f9aSHarsh Prateek Bora 1911331d0acSHarsh Prateek Bora typedef struct SpaprMachineStateNested { 1921331d0acSHarsh Prateek Bora uint64_t ptcr; 19321a8d22fSHarsh Prateek Bora uint8_t api; 19421a8d22fSHarsh Prateek Bora #define NESTED_API_KVM_HV 1 195bb23bcceSHarsh Prateek Bora #define NESTED_API_PAPR 2 19671c33ef0SHarsh Prateek Bora bool capabilities_set; 19771c33ef0SHarsh Prateek Bora uint32_t pvr_base; 198f5605626SHarsh Prateek Bora GHashTable *guests; 1991331d0acSHarsh Prateek Bora } SpaprMachineStateNested; 2001331d0acSHarsh Prateek Bora 201f5605626SHarsh Prateek Bora typedef struct SpaprMachineStateNestedGuest { 202f5605626SHarsh Prateek Bora uint32_t pvr_logical; 203c6664be0SHarsh Prateek Bora unsigned long nr_vcpus; 2044a575f9aSHarsh Prateek Bora uint64_t parttbl[2]; 2054a575f9aSHarsh Prateek Bora uint64_t tb_offset; 206c6664be0SHarsh Prateek Bora struct SpaprMachineStateNestedGuestVcpu *vcpus; 207f5605626SHarsh Prateek Bora } SpaprMachineStateNestedGuest; 208f5605626SHarsh Prateek Bora 20971c33ef0SHarsh Prateek Bora /* Nested PAPR API related macros */ 21071c33ef0SHarsh Prateek Bora #define H_GUEST_CAPABILITIES_COPY_MEM 0x8000000000000000 21171c33ef0SHarsh Prateek Bora #define H_GUEST_CAPABILITIES_P9_MODE 0x4000000000000000 21271c33ef0SHarsh Prateek Bora #define H_GUEST_CAPABILITIES_P10_MODE 0x2000000000000000 21371c33ef0SHarsh Prateek Bora #define H_GUEST_CAP_VALID_MASK (H_GUEST_CAPABILITIES_P10_MODE | \ 21471c33ef0SHarsh Prateek Bora H_GUEST_CAPABILITIES_P9_MODE) 21571c33ef0SHarsh Prateek Bora #define H_GUEST_CAP_COPY_MEM_BMAP 0 21671c33ef0SHarsh Prateek Bora #define H_GUEST_CAP_P9_MODE_BMAP 1 21771c33ef0SHarsh Prateek Bora #define H_GUEST_CAP_P10_MODE_BMAP 2 218f5605626SHarsh Prateek Bora #define PAPR_NESTED_GUEST_MAX 4096 219f5605626SHarsh Prateek Bora #define H_GUEST_DELETE_ALL_FLAG 0x8000000000000000ULL 220c6664be0SHarsh Prateek Bora #define PAPR_NESTED_GUEST_VCPU_MAX 2048 2214a575f9aSHarsh Prateek Bora #define VCPU_OUT_BUF_MIN_SZ 0x80ULL 2224a575f9aSHarsh Prateek Bora #define HVMASK_DEFAULT 0xffffffffffffffff 2234a575f9aSHarsh Prateek Bora #define HVMASK_LPCR 0x0070000003820800 2244a575f9aSHarsh Prateek Bora #define HVMASK_MSR 0xEBFFFFFFFFBFEFFF 2254a575f9aSHarsh Prateek Bora #define HVMASK_HDEXCR 0x00000000FFFFFFFF 2264a575f9aSHarsh Prateek Bora #define HVMASK_TB_OFFSET 0x000000FFFFFFFFFF 22764c43909SHarsh Prateek Bora #define GSB_MAX_BUF_SIZE (1024 * 1024) 22864c43909SHarsh Prateek Bora #define H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE 0x8000000000000000 22964c43909SHarsh Prateek Bora #define GUEST_STATE_REQUEST_GUEST_WIDE 0x1 23064c43909SHarsh Prateek Bora #define GUEST_STATE_REQUEST_SET 0x2 2314a575f9aSHarsh Prateek Bora 2324a575f9aSHarsh Prateek Bora /* 2334a575f9aSHarsh Prateek Bora * As per ISA v3.1B, following bits are reserved: 2344a575f9aSHarsh Prateek Bora * 0:2 2354a575f9aSHarsh Prateek Bora * 4:57 (ISA mentions bit 58 as well but it should be used for P10) 2364a575f9aSHarsh Prateek Bora * 61:63 (hence, haven't included PCR bits for v2.06 and v2.05 2374a575f9aSHarsh Prateek Bora * in LOW BITS) 2384a575f9aSHarsh Prateek Bora */ 2394a575f9aSHarsh Prateek Bora #define PCR_LOW_BITS (PCR_COMPAT_3_10 | PCR_COMPAT_3_00) 2404a575f9aSHarsh Prateek Bora #define HVMASK_PCR (~PCR_LOW_BITS) 2414a575f9aSHarsh Prateek Bora 2424a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT(i, sz, s, f, ptr, c) { \ 2434a575f9aSHarsh Prateek Bora .id = (i), \ 2444a575f9aSHarsh Prateek Bora .size = (sz), \ 2454a575f9aSHarsh Prateek Bora .location = ptr, \ 2464a575f9aSHarsh Prateek Bora .offset = offsetof(struct s, f), \ 2474a575f9aSHarsh Prateek Bora .copy = (c) \ 2484a575f9aSHarsh Prateek Bora } 2494a575f9aSHarsh Prateek Bora 2504a575f9aSHarsh Prateek Bora #define GSBE_NESTED(i, sz, f, c) { \ 2514a575f9aSHarsh Prateek Bora .id = (i), \ 2524a575f9aSHarsh Prateek Bora .size = (sz), \ 2534a575f9aSHarsh Prateek Bora .location = get_guest_ptr, \ 2544a575f9aSHarsh Prateek Bora .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\ 2554a575f9aSHarsh Prateek Bora .copy = (c), \ 2564a575f9aSHarsh Prateek Bora .mask = HVMASK_DEFAULT \ 2574a575f9aSHarsh Prateek Bora } 2584a575f9aSHarsh Prateek Bora 2594a575f9aSHarsh Prateek Bora #define GSBE_NESTED_MSK(i, sz, f, c, m) { \ 2604a575f9aSHarsh Prateek Bora .id = (i), \ 2614a575f9aSHarsh Prateek Bora .size = (sz), \ 2624a575f9aSHarsh Prateek Bora .location = get_guest_ptr, \ 2634a575f9aSHarsh Prateek Bora .offset = offsetof(struct SpaprMachineStateNestedGuest, f),\ 2644a575f9aSHarsh Prateek Bora .copy = (c), \ 2654a575f9aSHarsh Prateek Bora .mask = (m) \ 2664a575f9aSHarsh Prateek Bora } 2674a575f9aSHarsh Prateek Bora 2684a575f9aSHarsh Prateek Bora #define GSBE_NESTED_VCPU(i, sz, f, c) { \ 2694a575f9aSHarsh Prateek Bora .id = (i), \ 2704a575f9aSHarsh Prateek Bora .size = (sz), \ 2714a575f9aSHarsh Prateek Bora .location = get_vcpu_ptr, \ 2724a575f9aSHarsh Prateek Bora .offset = offsetof(struct SpaprMachineStateNestedGuestVcpu, f),\ 2734a575f9aSHarsh Prateek Bora .copy = (c), \ 2744a575f9aSHarsh Prateek Bora .mask = HVMASK_DEFAULT \ 2754a575f9aSHarsh Prateek Bora } 2764a575f9aSHarsh Prateek Bora 2774a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_NOP(i, sz) { \ 2784a575f9aSHarsh Prateek Bora .id = (i), \ 2794a575f9aSHarsh Prateek Bora .size = (sz), \ 2804a575f9aSHarsh Prateek Bora .location = NULL, \ 2814a575f9aSHarsh Prateek Bora .offset = 0, \ 2824a575f9aSHarsh Prateek Bora .copy = NULL, \ 2834a575f9aSHarsh Prateek Bora .mask = HVMASK_DEFAULT \ 2844a575f9aSHarsh Prateek Bora } 2854a575f9aSHarsh Prateek Bora 2864a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_NOP_DW(i) \ 2874a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_NOP(i, 8) 2884a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_NOP_W(i) \ 2894a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_NOP(i, 4) 2904a575f9aSHarsh Prateek Bora 2914a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_BASE(i, s, c) { \ 2924a575f9aSHarsh Prateek Bora .id = (i), \ 2934a575f9aSHarsh Prateek Bora .size = (s), \ 2944a575f9aSHarsh Prateek Bora .location = get_vcpu_state_ptr, \ 2954a575f9aSHarsh Prateek Bora .offset = 0, \ 2964a575f9aSHarsh Prateek Bora .copy = (c), \ 2974a575f9aSHarsh Prateek Bora .mask = HVMASK_DEFAULT \ 2984a575f9aSHarsh Prateek Bora } 2994a575f9aSHarsh Prateek Bora 3004a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_OFF(i, s, f, c) { \ 3014a575f9aSHarsh Prateek Bora .id = (i), \ 3024a575f9aSHarsh Prateek Bora .size = (s), \ 3034a575f9aSHarsh Prateek Bora .location = get_vcpu_state_ptr, \ 3044a575f9aSHarsh Prateek Bora .offset = offsetof(struct nested_ppc_state, f), \ 3054a575f9aSHarsh Prateek Bora .copy = (c), \ 3064a575f9aSHarsh Prateek Bora .mask = HVMASK_DEFAULT \ 3074a575f9aSHarsh Prateek Bora } 3084a575f9aSHarsh Prateek Bora 3094a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_MSK(i, s, f, c, m) { \ 3104a575f9aSHarsh Prateek Bora .id = (i), \ 3114a575f9aSHarsh Prateek Bora .size = (s), \ 3124a575f9aSHarsh Prateek Bora .location = get_vcpu_state_ptr, \ 3134a575f9aSHarsh Prateek Bora .offset = offsetof(struct nested_ppc_state, f), \ 3144a575f9aSHarsh Prateek Bora .copy = (c), \ 3154a575f9aSHarsh Prateek Bora .mask = (m) \ 3164a575f9aSHarsh Prateek Bora } 3174a575f9aSHarsh Prateek Bora 3184a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_ENV_QW(i, f) \ 3194a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_OFF(i, 16, f, copy_state_16to16) 3204a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_ENV_DW(i, f) \ 3214a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_OFF(i, 8, f, copy_state_8to8) 3224a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_ENV_W(i, f) \ 3234a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to8) 3244a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_ENV_WW(i, f) \ 3254a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_OFF(i, 4, f, copy_state_4to4) 3264a575f9aSHarsh Prateek Bora #define GSE_ENV_DWM(i, f, m) \ 3274a575f9aSHarsh Prateek Bora GUEST_STATE_ELEMENT_MSK(i, 8, f, copy_state_8to8, m) 32871c33ef0SHarsh Prateek Bora 32964c43909SHarsh Prateek Bora struct guest_state_element { 33064c43909SHarsh Prateek Bora uint16_t id; 33164c43909SHarsh Prateek Bora uint16_t size; 33264c43909SHarsh Prateek Bora uint8_t value[]; 33364c43909SHarsh Prateek Bora } QEMU_PACKED; 33464c43909SHarsh Prateek Bora 33564c43909SHarsh Prateek Bora struct guest_state_buffer { 33664c43909SHarsh Prateek Bora uint32_t num_elements; 33764c43909SHarsh Prateek Bora struct guest_state_element elements[]; 33864c43909SHarsh Prateek Bora } QEMU_PACKED; 33964c43909SHarsh Prateek Bora 34064c43909SHarsh Prateek Bora /* Actual buffer plus some metadata about the request */ 34164c43909SHarsh Prateek Bora struct guest_state_request { 34264c43909SHarsh Prateek Bora struct guest_state_buffer *gsb; 34364c43909SHarsh Prateek Bora int64_t buf; 34464c43909SHarsh Prateek Bora int64_t len; 34564c43909SHarsh Prateek Bora uint16_t flags; 34664c43909SHarsh Prateek Bora }; 34764c43909SHarsh Prateek Bora 3486b8a0537SNicholas Piggin /* 3496b8a0537SNicholas Piggin * Register state for entering a nested guest with H_ENTER_NESTED. 3506b8a0537SNicholas Piggin * New member must be added at the end. 3516b8a0537SNicholas Piggin */ 3526b8a0537SNicholas Piggin struct kvmppc_hv_guest_state { 3536b8a0537SNicholas Piggin uint64_t version; /* version of this structure layout, must be first */ 3546b8a0537SNicholas Piggin uint32_t lpid; 3556b8a0537SNicholas Piggin uint32_t vcpu_token; 3566b8a0537SNicholas Piggin /* These registers are hypervisor privileged (at least for writing) */ 3576b8a0537SNicholas Piggin uint64_t lpcr; 3586b8a0537SNicholas Piggin uint64_t pcr; 3596b8a0537SNicholas Piggin uint64_t amor; 3606b8a0537SNicholas Piggin uint64_t dpdes; 3616b8a0537SNicholas Piggin uint64_t hfscr; 3626b8a0537SNicholas Piggin int64_t tb_offset; 3636b8a0537SNicholas Piggin uint64_t dawr0; 3646b8a0537SNicholas Piggin uint64_t dawrx0; 3656b8a0537SNicholas Piggin uint64_t ciabr; 3666b8a0537SNicholas Piggin uint64_t hdec_expiry; 3676b8a0537SNicholas Piggin uint64_t purr; 3686b8a0537SNicholas Piggin uint64_t spurr; 3696b8a0537SNicholas Piggin uint64_t ic; 3706b8a0537SNicholas Piggin uint64_t vtb; 3716b8a0537SNicholas Piggin uint64_t hdar; 3726b8a0537SNicholas Piggin uint64_t hdsisr; 3736b8a0537SNicholas Piggin uint64_t heir; 3746b8a0537SNicholas Piggin uint64_t asdr; 3756b8a0537SNicholas Piggin /* These are OS privileged but need to be set late in guest entry */ 3766b8a0537SNicholas Piggin uint64_t srr0; 3776b8a0537SNicholas Piggin uint64_t srr1; 3786b8a0537SNicholas Piggin uint64_t sprg[4]; 3796b8a0537SNicholas Piggin uint64_t pidr; 3806b8a0537SNicholas Piggin uint64_t cfar; 3816b8a0537SNicholas Piggin uint64_t ppr; 3826b8a0537SNicholas Piggin /* Version 1 ends here */ 3836b8a0537SNicholas Piggin uint64_t dawr1; 3846b8a0537SNicholas Piggin uint64_t dawrx1; 3856b8a0537SNicholas Piggin /* Version 2 ends here */ 3866b8a0537SNicholas Piggin }; 3876b8a0537SNicholas Piggin 3886b8a0537SNicholas Piggin /* Latest version of hv_guest_state structure */ 3896b8a0537SNicholas Piggin #define HV_GUEST_STATE_VERSION 2 3906b8a0537SNicholas Piggin 3916b8a0537SNicholas Piggin /* Linux 64-bit powerpc pt_regs struct, used by nested HV */ 3926b8a0537SNicholas Piggin struct kvmppc_pt_regs { 3936b8a0537SNicholas Piggin uint64_t gpr[32]; 3946b8a0537SNicholas Piggin uint64_t nip; 3956b8a0537SNicholas Piggin uint64_t msr; 3966b8a0537SNicholas Piggin uint64_t orig_gpr3; /* Used for restarting system calls */ 3976b8a0537SNicholas Piggin uint64_t ctr; 3986b8a0537SNicholas Piggin uint64_t link; 3996b8a0537SNicholas Piggin uint64_t xer; 4006b8a0537SNicholas Piggin uint64_t ccr; 4016b8a0537SNicholas Piggin uint64_t softe; /* Soft enabled/disabled */ 4026b8a0537SNicholas Piggin uint64_t trap; /* Reason for being here */ 4036b8a0537SNicholas Piggin uint64_t dar; /* Fault registers */ 4046b8a0537SNicholas Piggin uint64_t dsisr; /* on 4xx/Book-E used for ESR */ 4056b8a0537SNicholas Piggin uint64_t result; /* Result of a system call */ 4066b8a0537SNicholas Piggin }; 4076b8a0537SNicholas Piggin 4086b8a0537SNicholas Piggin /* 4096b8a0537SNicholas Piggin * nested_ppc_state is used to save the host CPU state before switching it to 4106b8a0537SNicholas Piggin * the guest CPU state, to be restored on H_ENTER_NESTED exit. 4116b8a0537SNicholas Piggin */ 4126b8a0537SNicholas Piggin struct nested_ppc_state { 4136b8a0537SNicholas Piggin uint64_t gpr[32]; 4146b8a0537SNicholas Piggin uint64_t lr; 4156b8a0537SNicholas Piggin uint64_t ctr; 4166b8a0537SNicholas Piggin uint64_t cfar; 4176b8a0537SNicholas Piggin uint64_t msr; 4186b8a0537SNicholas Piggin uint64_t nip; 4196b8a0537SNicholas Piggin uint32_t cr; 4206b8a0537SNicholas Piggin 4216b8a0537SNicholas Piggin uint64_t xer; 4226b8a0537SNicholas Piggin 4236b8a0537SNicholas Piggin uint64_t lpcr; 4246b8a0537SNicholas Piggin uint64_t lpidr; 4256b8a0537SNicholas Piggin uint64_t pidr; 4266b8a0537SNicholas Piggin uint64_t pcr; 4276b8a0537SNicholas Piggin uint64_t dpdes; 4286b8a0537SNicholas Piggin uint64_t hfscr; 4296b8a0537SNicholas Piggin uint64_t srr0; 4306b8a0537SNicholas Piggin uint64_t srr1; 4316b8a0537SNicholas Piggin uint64_t sprg0; 4326b8a0537SNicholas Piggin uint64_t sprg1; 4336b8a0537SNicholas Piggin uint64_t sprg2; 4346b8a0537SNicholas Piggin uint64_t sprg3; 4356b8a0537SNicholas Piggin uint64_t ppr; 4366b8a0537SNicholas Piggin 4376b8a0537SNicholas Piggin int64_t tb_offset; 438bb23bcceSHarsh Prateek Bora /* Nested PAPR API */ 439bb23bcceSHarsh Prateek Bora uint64_t amor; 440bb23bcceSHarsh Prateek Bora uint64_t dawr0; 441bb23bcceSHarsh Prateek Bora uint64_t dawrx0; 442bb23bcceSHarsh Prateek Bora uint64_t ciabr; 443bb23bcceSHarsh Prateek Bora uint64_t purr; 444bb23bcceSHarsh Prateek Bora uint64_t spurr; 445bb23bcceSHarsh Prateek Bora uint64_t ic; 446bb23bcceSHarsh Prateek Bora uint64_t vtb; 447bb23bcceSHarsh Prateek Bora uint64_t hdar; 448bb23bcceSHarsh Prateek Bora uint64_t hdsisr; 449bb23bcceSHarsh Prateek Bora uint64_t heir; 450bb23bcceSHarsh Prateek Bora uint64_t asdr; 451bb23bcceSHarsh Prateek Bora uint64_t dawr1; 452bb23bcceSHarsh Prateek Bora uint64_t dawrx1; 453bb23bcceSHarsh Prateek Bora uint64_t dexcr; 454bb23bcceSHarsh Prateek Bora uint64_t hdexcr; 455bb23bcceSHarsh Prateek Bora uint64_t hashkeyr; 456bb23bcceSHarsh Prateek Bora uint64_t hashpkeyr; 457bb23bcceSHarsh Prateek Bora ppc_vsr_t vsr[64] QEMU_ALIGNED(16); 458bb23bcceSHarsh Prateek Bora uint64_t ebbhr; 459bb23bcceSHarsh Prateek Bora uint64_t tar; 460bb23bcceSHarsh Prateek Bora uint64_t ebbrr; 461bb23bcceSHarsh Prateek Bora uint64_t bescr; 462bb23bcceSHarsh Prateek Bora uint64_t iamr; 463bb23bcceSHarsh Prateek Bora uint64_t amr; 464bb23bcceSHarsh Prateek Bora uint64_t uamor; 465bb23bcceSHarsh Prateek Bora uint64_t dscr; 466bb23bcceSHarsh Prateek Bora uint64_t fscr; 467bb23bcceSHarsh Prateek Bora uint64_t pspb; 468bb23bcceSHarsh Prateek Bora uint64_t ctrl; 469bb23bcceSHarsh Prateek Bora uint64_t vrsave; 470bb23bcceSHarsh Prateek Bora uint64_t dar; 471bb23bcceSHarsh Prateek Bora uint64_t dsisr; 472bb23bcceSHarsh Prateek Bora uint64_t pmc1; 473bb23bcceSHarsh Prateek Bora uint64_t pmc2; 474bb23bcceSHarsh Prateek Bora uint64_t pmc3; 475bb23bcceSHarsh Prateek Bora uint64_t pmc4; 476bb23bcceSHarsh Prateek Bora uint64_t pmc5; 477bb23bcceSHarsh Prateek Bora uint64_t pmc6; 478bb23bcceSHarsh Prateek Bora uint64_t mmcr0; 479bb23bcceSHarsh Prateek Bora uint64_t mmcr1; 480bb23bcceSHarsh Prateek Bora uint64_t mmcr2; 481bb23bcceSHarsh Prateek Bora uint64_t mmcra; 482bb23bcceSHarsh Prateek Bora uint64_t sdar; 483bb23bcceSHarsh Prateek Bora uint64_t siar; 484bb23bcceSHarsh Prateek Bora uint64_t sier; 485bb23bcceSHarsh Prateek Bora uint32_t vscr; 486bb23bcceSHarsh Prateek Bora uint64_t fpscr; 4874a575f9aSHarsh Prateek Bora int64_t dec_expiry_tb; 4884a575f9aSHarsh Prateek Bora }; 4894a575f9aSHarsh Prateek Bora 4904a575f9aSHarsh Prateek Bora struct SpaprMachineStateNestedGuestVcpuRunBuf { 4914a575f9aSHarsh Prateek Bora uint64_t addr; 4924a575f9aSHarsh Prateek Bora uint64_t size; 4936b8a0537SNicholas Piggin }; 4946b8a0537SNicholas Piggin 495c6664be0SHarsh Prateek Bora typedef struct SpaprMachineStateNestedGuestVcpu { 496c6664be0SHarsh Prateek Bora bool enabled; 497c6664be0SHarsh Prateek Bora struct nested_ppc_state state; 4984a575f9aSHarsh Prateek Bora struct SpaprMachineStateNestedGuestVcpuRunBuf runbufin; 4994a575f9aSHarsh Prateek Bora struct SpaprMachineStateNestedGuestVcpuRunBuf runbufout; 5004a575f9aSHarsh Prateek Bora int64_t tb_offset; 5014a575f9aSHarsh Prateek Bora uint64_t hdecr_expiry_tb; 502c6664be0SHarsh Prateek Bora } SpaprMachineStateNestedGuestVcpu; 503c6664be0SHarsh Prateek Bora 5044a575f9aSHarsh Prateek Bora struct guest_state_element_type { 5054a575f9aSHarsh Prateek Bora uint16_t id; 5064a575f9aSHarsh Prateek Bora int size; 5074a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_TYPE_FLAG_GUEST_WIDE 0x1 5084a575f9aSHarsh Prateek Bora #define GUEST_STATE_ELEMENT_TYPE_FLAG_READ_ONLY 0x2 5094a575f9aSHarsh Prateek Bora uint16_t flags; 5104a575f9aSHarsh Prateek Bora void *(*location)(SpaprMachineStateNestedGuest *, target_ulong); 5114a575f9aSHarsh Prateek Bora size_t offset; 5124a575f9aSHarsh Prateek Bora void (*copy)(void *, void *, bool); 5134a575f9aSHarsh Prateek Bora uint64_t mask; 5144a575f9aSHarsh Prateek Bora }; 5154a575f9aSHarsh Prateek Bora 5166b8a0537SNicholas Piggin void spapr_exit_nested(PowerPCCPU *cpu, int excp); 5171331d0acSHarsh Prateek Bora typedef struct SpaprMachineState SpaprMachineState; 518c2813a35SHarsh Prateek Bora bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, 519c2813a35SHarsh Prateek Bora target_ulong lpid, ppc_v3_pate_t *entry); 52021a8d22fSHarsh Prateek Bora uint8_t spapr_nested_api(SpaprMachineState *spapr); 5214a575f9aSHarsh Prateek Bora void spapr_nested_gsb_init(void); 522*98823ce0SHarsh Prateek Bora bool spapr_get_pate_nested_papr(SpaprMachineState *spapr, PowerPCCPU *cpu, 523*98823ce0SHarsh Prateek Bora target_ulong lpid, ppc_v3_pate_t *entry); 5246b8a0537SNicholas Piggin #endif /* HW_SPAPR_NESTED_H */ 525