12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
26d91782fSAndrew Lunn /*
36d91782fSAndrew Lunn * Marvell 88E6xxx SERDES manipulation, via SMI bus
46d91782fSAndrew Lunn *
56d91782fSAndrew Lunn * Copyright (c) 2008 Marvell Semiconductor
66d91782fSAndrew Lunn *
76d91782fSAndrew Lunn * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
86d91782fSAndrew Lunn */
96d91782fSAndrew Lunn
106d91782fSAndrew Lunn #ifndef _MV88E6XXX_SERDES_H
116d91782fSAndrew Lunn #define _MV88E6XXX_SERDES_H
126d91782fSAndrew Lunn
134d5f2ba7SVivien Didelot #include "chip.h"
146d91782fSAndrew Lunn
1505407b0eSRussell King (Oracle) struct phylink_link_state;
1605407b0eSRussell King (Oracle)
176d91782fSAndrew Lunn #define MV88E6352_ADDR_SERDES 0x0f
186d91782fSAndrew Lunn #define MV88E6352_SERDES_PAGE_FIBER 0x01
194382172fSAndrew Lunn #define MV88E6352_SERDES_IRQ 0x0b
204382172fSAndrew Lunn #define MV88E6352_SERDES_INT_ENABLE 0x12
214382172fSAndrew Lunn #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
224382172fSAndrew Lunn #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
234382172fSAndrew Lunn #define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
244382172fSAndrew Lunn #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
254382172fSAndrew Lunn #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
264382172fSAndrew Lunn #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
274382172fSAndrew Lunn #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
284382172fSAndrew Lunn #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
294382172fSAndrew Lunn #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
304382172fSAndrew Lunn #define MV88E6352_SERDES_INT_STATUS 0x13
314382172fSAndrew Lunn
32926eae60SHolger Brunck #define MV88E6352_SERDES_SPEC_CTRL2 0x1a
33926eae60SHolger Brunck #define MV88E6352_SERDES_OUT_AMP_MASK 0x0007
346d91782fSAndrew Lunn
35d3cf7d8fSMarek Behún #define MV88E6341_PORT5_LANE 0x15
365bafeb6eSMarek Behún
376335e9f2SAndrew Lunn #define MV88E6390_PORT9_LANE0 0x09
386335e9f2SAndrew Lunn #define MV88E6390_PORT9_LANE1 0x12
396335e9f2SAndrew Lunn #define MV88E6390_PORT9_LANE2 0x13
406335e9f2SAndrew Lunn #define MV88E6390_PORT9_LANE3 0x14
416335e9f2SAndrew Lunn #define MV88E6390_PORT10_LANE0 0x0a
426335e9f2SAndrew Lunn #define MV88E6390_PORT10_LANE1 0x15
436335e9f2SAndrew Lunn #define MV88E6390_PORT10_LANE2 0x16
446335e9f2SAndrew Lunn #define MV88E6390_PORT10_LANE3 0x17
456335e9f2SAndrew Lunn
466335e9f2SAndrew Lunn /* 10GBASE-R and 10GBASE-X4/X2 */
47bf604bc9SRussell King #define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
487019bba4SRussell King #define MV88E6390_10G_STAT1 (0x1000 + MDIO_STAT1)
49e5b732a2SRussell King (Oracle) #define MV88E6390_10G_INT_ENABLE 0x9001
50e5b732a2SRussell King (Oracle) #define MV88E6390_10G_INT_LINK_DOWN BIT(3)
51e5b732a2SRussell King (Oracle) #define MV88E6390_10G_INT_LINK_UP BIT(2)
52e5b732a2SRussell King (Oracle) #define MV88E6390_10G_INT_STATUS 0x9003
53de776d0dSPavana Sharma #define MV88E6393X_10G_INT_ENABLE 0x9000
54de776d0dSPavana Sharma #define MV88E6393X_10G_INT_LINK_CHANGE BIT(2)
55de776d0dSPavana Sharma #define MV88E6393X_10G_INT_STATUS 0x9001
566335e9f2SAndrew Lunn
574a562127SMichal Smulski /* USXGMII */
584a562127SMichal Smulski #define MV88E6390_USXGMII_LP_STATUS 0xf0a2
594a562127SMichal Smulski #define MV88E6390_USXGMII_PHY_STATUS 0xf0a6
604a562127SMichal Smulski
616335e9f2SAndrew Lunn /* 1000BASE-X and SGMII */
624c8b7350SRussell King #define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
637e0e6243SRussell King #define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR)
64a5a6858bSRussell King #define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE)
65a5a6858bSRussell King #define MV88E6390_SGMII_LPA (0x2000 + MII_LPA)
66efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_ENABLE 0xa001
67efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
68efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
69efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
70efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
71efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
72efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_LINK_UP BIT(9)
73efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
74efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
75efd1ba6aSAndrew Lunn #define MV88E6390_SGMII_INT_STATUS 0xa002
7672d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS 0xa003
7772d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
7872d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
7972d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
8072d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
8172d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
8272d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
8372d8b4fdSHeiner Kallweit #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
84a5a6858bSRussell King #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3)
85a5a6858bSRussell King #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
866335e9f2SAndrew Lunn
870df95287SNikita Yushchenko /* Packet generator pad packet checker */
880df95287SNikita Yushchenko #define MV88E6390_PG_CONTROL 0xf010
890df95287SNikita Yushchenko #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
900df95287SNikita Yushchenko
91de776d0dSPavana Sharma #define MV88E6393X_PORT0_LANE 0x00
92de776d0dSPavana Sharma #define MV88E6393X_PORT9_LANE 0x09
93de776d0dSPavana Sharma #define MV88E6393X_PORT10_LANE 0x0a
94de776d0dSPavana Sharma
95de776d0dSPavana Sharma /* Port Operational Configuration */
96de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC 0xf002
97de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000
98de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001
99de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002
100de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003
101de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_5GBASER 0x0004
102de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_10GBASER 0x0005
103de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY 0x0006
104de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC 0x0007
105de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PCS_MASK 0x0007
106de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_RESET BIT(15)
107de776d0dSPavana Sharma #define MV88E6393X_SERDES_POC_PDOWN BIT(5)
108163000dbSMarek Behún #define MV88E6393X_SERDES_POC_AN BIT(3)
1097527d662SMarek Behún #define MV88E6393X_SERDES_CTRL1 0xf003
1107527d662SMarek Behún #define MV88E6393X_SERDES_CTRL1_TX_PDOWN BIT(9)
1117527d662SMarek Behún #define MV88E6393X_SERDES_CTRL1_RX_PDOWN BIT(8)
112de776d0dSPavana Sharma
113de776d0dSPavana Sharma #define MV88E6393X_ERRATA_4_8_REG 0xF074
114de776d0dSPavana Sharma #define MV88E6393X_ERRATA_4_8_BIT BIT(14)
115de776d0dSPavana Sharma
11605407b0eSRussell King (Oracle) int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa,
11705407b0eSRussell King (Oracle) u16 status, struct phylink_link_state *state);
11805407b0eSRussell King (Oracle)
119193c5b26SPavana Sharma int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
120193c5b26SPavana Sharma int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
121193c5b26SPavana Sharma int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
122de776d0dSPavana Sharma int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
1234241ef52SVivien Didelot unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
1244241ef52SVivien Didelot int port);
1254241ef52SVivien Didelot unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
1264241ef52SVivien Didelot int port);
127cda9f4aaSAndrew Lunn int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
12865f60e45SAndrew Lunn int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
129cda9f4aaSAndrew Lunn int port, uint8_t *data);
130*f6791424STobias Waldekranz size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
131cda9f4aaSAndrew Lunn uint64_t *data);
1320df95287SNikita Yushchenko int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
1330df95287SNikita Yushchenko int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
1340df95287SNikita Yushchenko int port, uint8_t *data);
135*f6791424STobias Waldekranz size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
1360df95287SNikita Yushchenko uint64_t *data);
1374382172fSAndrew Lunn
138d3f88a24SAndrew Lunn int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
139d3f88a24SAndrew Lunn void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
140bf3504ceSAndrew Lunn int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
141bf3504ceSAndrew Lunn void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
142d3f88a24SAndrew Lunn
143926eae60SHolger Brunck int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
144926eae60SHolger Brunck int val);
145926eae60SHolger Brunck
146193c5b26SPavana Sharma /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip * chip,int port)147193c5b26SPavana Sharma static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
1485122d4ecSVivien Didelot int port)
1495122d4ecSVivien Didelot {
1505122d4ecSVivien Didelot if (!chip->info->ops->serdes_get_lane)
151193c5b26SPavana Sharma return -EOPNOTSUPP;
1525122d4ecSVivien Didelot
1535122d4ecSVivien Didelot return chip->info->ops->serdes_get_lane(chip, port);
1545122d4ecSVivien Didelot }
1555122d4ecSVivien Didelot
1564241ef52SVivien Didelot static inline unsigned int
mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip * chip,int port)1574241ef52SVivien Didelot mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
1584241ef52SVivien Didelot {
1594241ef52SVivien Didelot if (!chip->info->ops->serdes_irq_mapping)
1604241ef52SVivien Didelot return 0;
1614241ef52SVivien Didelot
1624241ef52SVivien Didelot return chip->info->ops->serdes_irq_mapping(chip, port);
1634241ef52SVivien Didelot }
164734447d4SAndrew Lunn
1654aabe35cSRussell King (Oracle) extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops;
16685764555SRussell King extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops;
167e5b732a2SRussell King (Oracle) extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops;
168e5b732a2SRussell King (Oracle) extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops;
1694aabe35cSRussell King (Oracle)
1706d91782fSAndrew Lunn #endif
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