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/openbmc/u-boot/include/configs/
H A DMCR3000.h13 "sdram_type=SDRAM\0" \
14 "flash_type=AM29LV160DB\0" \
15 "loadaddr=0x400000\0" \
16 "filename=uImage.lzma\0" \
17 "nfsroot=/opt/ofs\0" \
18 "dhcp_ip=ip=:::::eth0:dhcp\0" \
19 "console_args=console=ttyCPM0,115200N8\0" \
25 "bootm 0x04060000 - 0x04050000\0" \
32 "tftp 0xf00000 mcr3000.dtb;" \
33 "bootm ${loadaddr} - 0xf00000\0" \
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-som-p0.dtsi16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0x00000000 0x80000000>;
26 reg = <0x00 0x9e800000 0x00 0x01800000>;
27 alignment = <0x1000>;
33 reg = <0x00 0xa0000000 0x00 0x100000>;
39 reg = <0x00 0xa0100000 0x00 0xf00000>;
45 reg = <0x00 0xa1000000 0x00 0x100000>;
51 reg = <0x00 0xa1100000 0x00 0xf00000>;
57 reg = <0x00 0xa2000000 0x00 0x100000>;
63 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-j784s4-evm.dts35 reg = <0x00 0x80000000 0x00 0x80000000>,
36 <0x08 0x80000000 0x07 0x80000000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>;
51 reg = <0x00 0xa0000000 0x00 0x100000>;
57 reg = <0x00 0xa0100000 0x00 0xf00000>;
63 reg = <0x00 0xa1000000 0x00 0x100000>;
69 reg = <0x00 0xa1100000 0x00 0xf00000>;
75 reg = <0x00 0xa2000000 0x00 0x100000>;
81 reg = <0x00 0xa2100000 0x00 0xf00000>;
87 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-am642-tqma64xxl.dtsi19 reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
29 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>;
36 reg = <0x00 0xa0000000 0x00 0x100000>;
42 reg = <0x00 0xa0100000 0x00 0xf00000>;
48 reg = <0x00 0xa1000000 0x00 0x100000>;
54 reg = <0x00 0xa1100000 0x00 0xf00000>;
60 reg = <0x00 0xa2000000 0x00 0x100000>;
66 reg = <0x00 0xa2100000 0x00 0xf00000>;
72 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
H A Dk3-j721e-beagleboneai64.dts40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
41 <0x00000008 0x80000000 0x00000000 0x80000000>;
50 reg = <0x00 0x9e800000 0x00 0x01800000>;
56 reg = <0x00 0xa0000000 0x00 0x100000>;
62 reg = <0x00 0xa0100000 0x00 0xf00000>;
68 reg = <0x00 0xa1000000 0x00 0x100000>;
74 reg = <0x00 0xa1100000 0x00 0xf00000>;
80 reg = <0x00 0xa2000000 0x00 0x100000>;
86 reg = <0x00 0xa2100000 0x00 0xf00000>;
92 reg = <0x00 0xa3000000 0x00 0x100000>;
[all …]
H A Dk3-j721e-sk.dts35 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
36 <0x00000008 0x80000000 0x00000000 0x80000000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>;
46 alignment = <0x1000>;
52 reg = <0x00 0xa0000000 0x00 0x100000>;
58 reg = <0x00 0xa0100000 0x00 0xf00000>;
64 reg = <0x00 0xa1000000 0x00 0x100000>;
70 reg = <0x00 0xa1100000 0x00 0xf00000>;
76 reg = <0x00 0xa2000000 0x00 0x100000>;
82 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dbrcm,bcm4908-partitions.yaml33 "^partition@[0-9a-f]+$":
53 partition@0 {
55 reg = <0x0 0x100000>;
60 reg = <0x100000 0xf00000>;
65 reg = <0x1000000 0xf00000>;
70 reg = <0x1f00000 0x100000>;
H A Dlinksys,ns-partitions.yaml34 "^partition@[0-9a-f]+$":
56 partition@0 {
58 reg = <0x0 0x100000>;
64 reg = <0x100000 0x100000>;
69 reg = <0x200000 0xf00000>;
74 reg = <0x1100000 0xf00000>;
H A Dfixed-partitions.yaml33 "@[0-9a-f]+$":
59 partition@0 {
61 reg = <0x0000000 0x100000>;
66 reg = <0x0100000 0x200000>;
77 partition@0 {
79 reg = <0x00000000 0x1 0x00000000>;
91 partition@0 {
93 reg = <0x0 0x00000000 0x2 0x00000000>;
99 reg = <0x2 0x00000000 0x1 0x00000000>;
109 partition@0 {
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-80x0.dtsi24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
H A Dcn9130.dtsi29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
H A Darmada-70x0.dtsi22 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
23 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/
H A D0025-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch24 …m $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf0…
25 …m $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf0…
35 CONFIG_SYS_BOOTM_LEN=0x800000
58 @@ -65,4 +64,12 @@ CONFIG_FFA_SHARED_MM_BUF_OFFSET=0
59 CONFIG_FFA_SHARED_MM_BUF_ADDR=0x02000000
H A D0031-corstone1000-detect-inflated-kernel-size.patch22 …m $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf0…
23 …oading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $k…
H A D0018-corstone1000-add-compressed-kernel-support.patch27 … kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; u…
28 …m $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf0…
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-slave.dtsi62 ranges = <0x0 0x0 0xf4000000 0x2000000>;
64 cps_ethernet: ethernet@0 {
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
74 port-id = <0>;
75 gop-port-id = <0>;
96 #size-cells = <0>;
98 reg = <0x12a200 0x10>;
104 reg = <0x440000 0x1000>;
125 reg = <0x440000 0x20>;
127 max-func = <0xf>;
[all …]
H A Darmada-cp110-master.dtsi62 ranges = <0x0 0x0 0xf2000000 0x2000000>;
64 cpm_ethernet: ethernet@0 {
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
74 port-id = <0>;
75 gop-port-id = <0>;
96 #size-cells = <0>;
98 reg = <0x12a200 0x10>;
104 reg = <0x440000 0x1000>;
126 reg = <0x440000 0x20>;
128 max-func = <0xf>;
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53340-ubnt-unifi-switch8.dts22 memory@0 {
24 reg = <0x00000000 0x08000000>,
25 <0x68000000 0x08000000>;
35 bspi-sel = <0>;
37 flash: flash@0 {
39 reg = <0>;
46 partition@0 {
48 reg = <0x0 0xc0000>;
53 reg = <0xc0000 0x10000>;
58 reg = <0xd0000 0x10000>;
[all …]

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