Lines Matching +full:0 +full:xf00000
35 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
36 <0x00000008 0x80000000 0x00000000 0x80000000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>;
46 alignment = <0x1000>;
52 reg = <0x00 0xa0000000 0x00 0x100000>;
58 reg = <0x00 0xa0100000 0x00 0xf00000>;
64 reg = <0x00 0xa1000000 0x00 0x100000>;
70 reg = <0x00 0xa1100000 0x00 0xf00000>;
76 reg = <0x00 0xa2000000 0x00 0x100000>;
82 reg = <0x00 0xa2100000 0x00 0xf00000>;
88 reg = <0x00 0xa3000000 0x00 0x100000>;
94 reg = <0x00 0xa3100000 0x00 0xf00000>;
100 reg = <0x00 0xa4000000 0x00 0x100000>;
106 reg = <0x00 0xa4100000 0x00 0xf00000>;
112 reg = <0x00 0xa5000000 0x00 0x100000>;
118 reg = <0x00 0xa5100000 0x00 0xf00000>;
124 reg = <0x00 0xa6000000 0x00 0x100000>;
130 reg = <0x00 0xa6100000 0x00 0xf00000>;
136 reg = <0x00 0xa7000000 0x00 0x100000>;
142 reg = <0x00 0xa7100000 0x00 0xf00000>;
148 reg = <0x00 0xa8000000 0x00 0x100000>;
154 reg = <0x00 0xa8100000 0x00 0xf00000>;
159 reg = <0x00 0xaa000000 0x00 0x01c00000>;
160 alignment = <0x1000>;
189 pinctrl-0 = <&vdd_mmc1_en_pins_default>;
202 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
209 states = <1800000 0x0>,
210 <3300000 0x1>;
219 pinctrl-0 = <&dp_pwr_en_pins_default>;
220 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */
243 pinctrl-0 = <&hdmi_hpd_pins_default>;
248 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>;
261 pinctrl-0 = <&hdmi_pdn_pins_default>;
264 ti,deskew = <0>;
268 #size-cells = <0>;
270 port@0 {
271 reg = <0>;
294 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
295 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
296 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
297 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
298 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
299 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
300 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
301 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
307 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
308 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
309 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
310 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
316 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
317 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
323 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
324 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
330 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
331 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
337 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
338 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
344 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
345 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
351 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
357 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
363 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */
369 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */
370 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */
371 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */
372 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */
373 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */
374 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */
375 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */
376 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */
377 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */
378 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */
379 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */
380 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */
381 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */
382 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */
383 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */
384 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */
385 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */
386 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */
387 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */
388 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */
389 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */
390 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */
391 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */
392 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */
393 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */
394 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */
395 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */
396 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */
402 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */
408 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
415 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */
421 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
422 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
428 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
429 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */
430 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
431 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
432 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
433 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
434 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
435 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
436 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
437 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
438 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
439 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
440 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
441 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
442 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
443 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
444 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
445 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
446 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
447 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
448 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
449 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
450 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
456 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
464 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
465 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
466 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
467 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
468 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
469 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
470 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
471 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
472 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
473 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
474 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
475 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
481 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
482 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
488 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
489 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
490 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
491 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
492 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
493 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
494 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
495 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
496 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
497 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
498 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
504 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
510 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
516 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
517 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
523 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
524 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
525 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
526 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
532 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
533 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
540 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */
549 pinctrl-0 = <&wkup_uart0_pins_default>;
555 pinctrl-0 = <&wkup_i2c0_pins_default>;
561 reg = <0x51>;
568 pinctrl-0 = <&mcu_uart0_pins_default>;
574 pinctrl-0 = <&main_uart0_pins_default>;
582 pinctrl-0 = <&main_uart1_pins_default>;
591 pinctrl-0 = <&main_mmc1_pins_default>;
599 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
601 flash@0 {
603 reg = <0x0>;
618 partition@0 {
620 reg = <0x0 0x80000>;
625 reg = <0x80000 0x200000>;
630 reg = <0x280000 0x400000>;
635 reg = <0x680000 0x40000>;
640 reg = <0x6c0000 0x100000>;
645 reg = <0x7c0000 0x40000>;
650 reg = <0x800000 0x37c0000>;
655 reg = <0x3fc0000 0x40000>;
664 pinctrl-0 = <&main_i2c0_pins_default>;
670 #size-cells = <0>;
671 reg = <0x71>;
674 i2c@0 {
676 #size-cells = <0>;
677 reg = <0>;
683 #size-cells = <0>;
692 pinctrl-0 = <&main_i2c1_pins_default>;
700 pinctrl-0 = <&main_i2c3_pins_default>;
706 #size-cells = <0>;
707 reg = <0x70>;
710 i2c@0 {
712 #size-cells = <0>;
713 reg = <0>;
719 #size-cells = <0>;
729 pinctrl-0 = <&main_i2c5_pins_default>;
736 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
742 pinctrl-0 = <&rpi_header_gpio1_pins_default>;
768 serdes3_usb_link: phy@0 {
769 reg = <0>;
771 #phy-cells = <0>;
778 torrent_phy_dp: phy@0 {
779 reg = <0>;
784 #phy-cells = <0>;
792 pinctrl-0 = <&dp0_pins_default>;
797 pinctrl-0 = <&main_usbss0_pins_default>;
812 #phy-cells = <0>;
820 pinctrl-0 = <&main_usbss1_pins_default>;
833 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
837 phy0: ethernet-phy@0 {
838 reg = <0>;
851 pinctrl-0 = <&dss_vout0_pins_default>;
865 #size-cells = <0>;
867 port@0 {
868 reg = <0>;
886 #size-cells = <0>;
888 port@0 {
889 reg = <0>;
904 serdes0_pcie_link: phy@0 {
905 reg = <0>;
907 #phy-cells = <0>;
914 serdes1_pcie_link: phy@0 {
915 reg = <0>;
917 #phy-cells = <0>;
926 pinctrl-0 = <&ekey_reset_pins_default>;
937 pinctrl-0 = <&mkey_reset_pins_default>;
954 ti,mbox-rx = <0 0 0>;
955 ti,mbox-tx = <1 0 0>;
959 ti,mbox-rx = <2 0 0>;
960 ti,mbox-tx = <3 0 0>;
969 ti,mbox-rx = <0 0 0>;
970 ti,mbox-tx = <1 0 0>;
974 ti,mbox-rx = <2 0 0>;
975 ti,mbox-tx = <3 0 0>;
984 ti,mbox-rx = <0 0 0>;
985 ti,mbox-tx = <1 0 0>;
989 ti,mbox-rx = <2 0 0>;
990 ti,mbox-tx = <3 0 0>;
998 mbox_c66_0: mbox-c66-0 {
999 ti,mbox-rx = <0 0 0>;
1000 ti,mbox-tx = <1 0 0>;
1004 ti,mbox-rx = <2 0 0>;
1005 ti,mbox-tx = <3 0 0>;
1013 mbox_c71_0: mbox-c71-0 {
1014 ti,mbox-rx = <0 0 0>;
1015 ti,mbox-tx = <1 0 0>;