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Searched +full:0 +full:xc0100000 (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/arm/mach-stm32mp/
H A DKconfig43 default 0xC0100000
47 DDR + 1MB (0xC0100000)
67 default 0x40010000
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu8.h65 #define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
66 #define SMU8_UNBCSR_START_ADDR 0xC0100000
68 #define SMN_MP1_SRAM_START_ADDR 0x10000000
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Daltr,tse.yaml116 reg = <0xc0100000 0x00000400>,
117 <0xc0101000 0x00000020>,
118 <0xc0102000 0x00000020>,
119 <0xc0103000 0x00000008>,
120 <0xc0104000 0x00000020>,
121 <0xc0105000 0x00000020>,
122 <0xc0106000 0x00000100>;
125 interrupts = <0 44 4>,<0 45 4>;
140 reg = <0x00001000 0x00000400>,
141 <0x00001460 0x00000020>,
[all …]
/openbmc/u-boot/include/
H A DMCD_dma.h76 u32 taskSize0; /* task size control 0. */
92 #define PTD_CTL_TSK_PRI 0x8000
93 #define PTD_CTL_COMM_PREFETCH 0x0001
96 #define TASK_CTL_EN 0x8000
97 #define TASK_CTL_VALID 0x4000
98 #define TASK_CTL_ALWAYS 0x2000
99 #define TASK_CTL_INIT_MASK 0x1f00
100 #define TASK_CTL_ASTRT 0x0080
101 #define TASK_CTL_HIPRITSKEN 0x0040
102 #define TASK_CTL_HLDINITNUM 0x0020
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dpage.h112 #define MEMORY_START 0UL
158 * Let the kernel be loaded at 64MB and KERNELBASE be 0xc0000000 (same as PAGE_OFFSET).
159 * In this case, we would be mapping 0 to 0xc0000000, and kernstart_addr = 64M
161 * Now __va(1MB) = (0x100000) - (0x4000000) + 0xc0000000
162 * = 0xbc100000 , which is wrong.
164 * Rather, it should be : 0xc0000000 + 0x100000 = 0xc0100000
218 (unsigned long)(x) & 0x0fffffffffffffffUL; \
265 #define is_kernel_addr(x) ((x) >= 0x8000000000000000ul)
280 #define PD_HUGE 0x8000000000000000UL
282 #define PD_HUGE 0x80000000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h10 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
11 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
12 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
17 #define SOC_VER_SLS1020 0x00
18 #define SOC_VER_LS1020 0x10
19 #define SOC_VER_LS1021 0x11
20 #define SOC_VER_LS1022 0x12
22 #define SOC_MAJOR_VER_1_0 0x1
23 #define SOC_MAJOR_VER_2_0 0x2
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_1_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_2_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_3_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_1_0_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]
H A Dsmu_7_0_1_d.h27 #define mmGCK_SMC_IND_INDEX 0x80
28 #define mmGCK0_GCK_SMC_IND_INDEX 0x80
29 #define mmGCK1_GCK_SMC_IND_INDEX 0x82
30 #define mmGCK2_GCK_SMC_IND_INDEX 0x84
31 #define mmGCK3_GCK_SMC_IND_INDEX 0x86
32 #define mmGCK_SMC_IND_DATA 0x81
33 #define mmGCK0_GCK_SMC_IND_DATA 0x81
34 #define mmGCK1_GCK_SMC_IND_DATA 0x83
35 #define mmGCK2_GCK_SMC_IND_DATA 0x85
36 #define mmGCK3_GCK_SMC_IND_DATA 0x87
[all …]