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/openbmc/u-boot/configs/
H A Dk2e_evm_defconfig3 CONFIG_SYS_TEXT_BASE=0xC000000
28 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
29 CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
H A Dk2l_evm_defconfig3 CONFIG_SYS_TEXT_BASE=0xC000000
28 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
29 CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
H A Dk2hk_evm_defconfig3 CONFIG_SYS_TEXT_BASE=0xC000000
28 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
29 CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
H A Dk2g_evm_defconfig3 CONFIG_SYS_TEXT_BASE=0xC000000
27 CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0"
28 CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)"
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/qemu/tests/qtest/
H A Dtpm-tis-device-swtpm-test.c24 uint64_t tpm_tis_base_addr = 0xc000000;
53 TestState ts = { 0 }; in main()
H A Dtpm-tis-device-test.c30 uint64_t tpm_tis_base_addr = 0xc000000;
/openbmc/qemu/tests/qemu-iotests/
H A D07026 seq=`basename $0`
35 trap "_cleanup; exit \$status" 0 1 2 3 15
45 # With the log replayed, the pattern 0xa5 extends to 0xc025000
46 # If the log was not replayed, it would only extend to 0xc000000
58 $QEMU_IO -r -c "read -pP 0xa5 0 18M" "$TEST_IMG" 2>&1 | _filter_testdir \
62 $QEMU_IO -c "read -pP 0xa5 0 18M" "$TEST_IMG" | _filter_qemu_io
71 $QEMU_IO -r -c "read -pP 0xa5 0 18M" "$TEST_IMG" 2>&1 | _filter_testdir \
84 status=0
/openbmc/u-boot/board/ti/ks2_evm/
H A DREADME113 Start address as 0xc000000, choose Type-size "32 bits" and click "Finish"
117 to be 0xc000000. From the "Run" top level menu, select "Free Run"
130 Hit any key to stop autoboot: 0
140 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
142 EVM using CCS", but using address 0x87000000.
145 setenv addr_uboot 0x87000000
146 setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000>
161 3. Load MLO binary from build folder on to DDR address 0x87000000
163 using CCS", but using address 0x87000000.
166 setenv filesize <size in hex of MLO rounded to hex 0x10000>
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
38 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
39 * 3. RF register 0x00-2E
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
47 #define rPMAC_TxStart 0x104
48 #define rPMAC_TxLegacySIG 0x108
49 #define rPMAC_TxHTSIG1 0x10c
50 #define rPMAC_TxHTSIG2 0x110
51 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
64 - const: sifive,plic-1.0.0
71 - const: sifive,plic-1.0.0
80 const: 0
160 #address-cells = <0>;
162 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
169 reg = <0xc000000 0x4000000>;
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
44 /* 3. RF register 0x00-2E */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
55 #define rPMAC_TxStart 0x104
56 #define rPMAC_TxLegacySIG 0x108
57 #define rPMAC_TxHTSIG1 0x10c
58 #define rPMAC_TxHTSIG2 0x110
59 #define rPMAC_PHYDebug 0x114
[all …]
/openbmc/u-boot/include/net/pfe_eth/pfe/
H A Dpfe_hw.h15 #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
17 #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
18 #define CLASS_DMEM_SIZE 0x00002000
19 #define CLASS_IMEM_SIZE 0x00008000
21 #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
23 #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
24 #define TMU_DMEM_SIZE 0x00000800
25 #define TMU_IMEM_SIZE 0x00002000
27 #define UTIL_DMEM_BASE_ADDR 0x00000000
28 #define UTIL_DMEM_SIZE 0x00002000
[all …]
/openbmc/u-boot/include/configs/
H A Dls2080a_common.h20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
29 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
30 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
31 #define CONFIG_ENV_SECT_SIZE 0x40000
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
57 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
59 * DDR controller use 0 as the base address for binding.
62 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
[all …]
H A Dls1088a_common.h29 #define LS1088ARDB_PB_BOARD 0x4A
34 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
39 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
42 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
43 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
52 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
53 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
55 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
75 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
86 * During booting, IFC is mapped at the region of 0x30000000.
[all …]
H A Dti_armv7_keystone2.h23 #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
31 #define SPL_MALLOC_F_SIZE 0
51 #define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
54 #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
142 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
144 #define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
146 #define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
150 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
158 #define CONFIG_SYS_NAND_MASK_CLE 0x4000
159 #define CONFIG_SYS_NAND_MASK_ALE 0x2000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7628a.dtsi10 #size-cells = <0>;
12 cpu@0 {
15 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>;
39 sysc: system-controller@0 {
41 reg = <0x0 0x60>;
46 reg = <0x60 0x8>;
48 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9m10g45ek.dts24 reg = <0x70000000 0x4000000>;
45 pinctrl-0 =
61 reg = <0x30>;
63 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
89 pinctrl-0 = <
94 slot@0 {
95 reg = <0>;
102 pinctrl-0 = <
107 slot@0 {
108 reg = <0>;
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_xcvr.h11 #define FSL_XCVR_MODE_SPDIF 0
16 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */
17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */
23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C00
24 #define FSL_XCVR_TX_FIFO_ADDR 0x0E00
26 #define FSL_XCVR_VERSION 0x00 /* Version */
27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */
28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */
29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */
30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
110 #clock-cells = <0>;
112 clock-frequency = <0>;
117 #clock-cells = <0>;
119 clock-frequency = <0>;
124 #clock-cells = <0>;
126 clock-frequency = <0>;
131 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9m10g45ek.dts22 reg = <0x70000000 0x4000000>;
42 timer@0 {
44 reg = <0>, <1>;
54 pinctrl-0 =
70 reg = <0x30>;
72 pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
98 pinctrl-0 = <
104 slot@0 {
105 reg = <0>;
112 pinctrl-0 = <
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/
H A Dreg.h7 #define REG_SYS_ISO_CTRL 0x0000
8 #define REG_SYS_FUNC_EN 0x0002
9 #define REG_APS_FSMCO 0x0004
10 #define REG_SYS_CLKR 0x0008
11 #define REG_9346CR 0x000A
12 #define REG_EE_VPD 0x000C
13 #define REG_AFE_MISC 0x0010
14 #define REG_SPS0_CTRL 0x0011
15 #define REG_SPS_OCP_CFG 0x0018
16 #define REG_RSV_CTRL 0x001C
[all …]

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