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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-etsec2-0.dtsi2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
38 #size-cells = <0>;
40 reg = <0x24000 0x1000 0xb0030 0x4>;
49 fsl,num_rx_queues = <0x8>;
50 fsl,num_tx_queues = <0x8>;
58 reg = <0xb0000 0x1000>;
59 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
H A Dqoriq-fman-0-10g-0.dtsi2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
60 interrupts = <101 2 0 0>;
H A Dqoriq-fman-1-10g-0.dtsi2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
H A Dqoriq-fman3-1-10g-0.dtsi2 * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
44 cell-index = <0x30>;
46 reg = <0xb0000 0x1000>;
51 cell-index = <0x8>;
53 reg = <0xf0000 0x1000>;
68 #size-cells = <0>;
70 reg = <0xf1000 0x1000>;
73 pcsphy14: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-0-10g-0.dtsi2 * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
44 cell-index = <0x30>;
46 reg = <0xb0000 0x1000>;
51 cell-index = <0x8>;
53 reg = <0xf0000 0x1000>;
68 #size-cells = <0>;
70 reg = <0xf1000 0x1000>;
73 pcsphy6: ethernet-phy@0 {
[all …]
/openbmc/linux/drivers/video/
H A Dscreen_info_generic.c12 memset(r, 0, sizeof(*r)); in resource_init_named()
37 case 0x0d: /* 320x200-4 */ in __screen_info_has_ega_gfx()
38 case 0x0e: /* 640x200-4 */ in __screen_info_has_ega_gfx()
39 case 0x0f: /* 640x350-1 */ in __screen_info_has_ega_gfx()
40 case 0x10: /* 640x350-4 */ in __screen_info_has_ega_gfx()
50 case 0x10: /* 640x480-1 */ in __screen_info_has_vga_gfx()
51 case 0x12: /* 640x480-4 */ in __screen_info_has_vga_gfx()
52 case 0x13: /* 320-200-8 */ in __screen_info_has_vga_gfx()
53 case 0x6a: /* 800x600-4 (VESA) */ in __screen_info_has_vga_gfx()
82 if (num > 0) in screen_info_resources()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dmarvell,armada-3700-rwtm-mailbox.txt13 reg = <0xb0000 0x100>;
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Dstr2mem_defs.h19 #define _STR2MEM_CRUN_BIT 0x100000
20 #define _STR2MEM_CMD_BITS 0x0F0000
21 #define _STR2MEM_COUNT_BITS 0x00FFFF
23 #define _STR2MEM_BLOCKS_CMD 0xA0000
24 #define _STR2MEM_PACKETS_CMD 0xB0000
25 #define _STR2MEM_BYTES_CMD 0xC0000
26 #define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000
28 #define _STR2MEM_SOFT_RESET_REG_ID 0
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-10g-0.dtsi3 * QorIQ FMan v3 10g port #0 device tree
11 cell-index = <0x10>;
13 reg = <0x90000 0x1000>;
18 cell-index = <0x30>;
20 reg = <0xb0000 0x1000>;
25 cell-index = <0x8>;
27 reg = <0xf0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xf1000 0x1000>;
38 pcsphy6: ethernet-phy@0 {
[all …]
/openbmc/u-boot/include/configs/
H A Dsama5d27_som1_ek.h18 #define CONFIG_SYS_SDRAM_BASE 0x20000000
19 #define CONFIG_SYS_SDRAM_SIZE 0x8000000
22 #define CONFIG_SYS_INIT_SP_ADDR 0x218000
28 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
38 #define CONFIG_ENV_SIZE 0x4000
40 #define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27…
41 "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
42 "bootz 0x22000000 - 0x21000000"
46 #define CONFIG_ENV_OFFSET 0xb0000
47 #define CONFIG_ENV_SIZE 0x10000
[all …]
/openbmc/u-boot/arch/x86/cpu/queensbay/
H A DKconfig47 default 0xfffb0000
52 The default base address of 0xfffb0000 indicates that the binary must
53 be located at offset 0xb0000 from the beginning of a 1MB flash device.
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-msm8998.yaml55 reg = <0x00100000 0xb0000>;
58 <0>;
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay2.h94 u8 res[0xc];
112 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
113 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
115 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
116 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
117 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
118 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
119 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
120 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
121 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
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/openbmc/qemu/hw/display/
H A Dcirrus_vga_internal.h32 #define CIRRUS_ID_CLGD5422 (0x23 << 2)
33 #define CIRRUS_ID_CLGD5426 (0x24 << 2)
34 #define CIRRUS_ID_CLGD5424 (0x25 << 2)
35 #define CIRRUS_ID_CLGD5428 (0x26 << 2)
36 #define CIRRUS_ID_CLGD5430 (0x28 << 2)
37 #define CIRRUS_ID_CLGD5434 (0x2A << 2)
38 #define CIRRUS_ID_CLGD5436 (0x2B << 2)
39 #define CIRRUS_ID_CLGD5446 (0x2E << 2)
58 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
60 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
/openbmc/linux/tools/perf/arch/s390/util/
H A Dauxtrace.c14 #define PERF_EVENT_CPUM_SF 0xB0000 /* Event: Basic-sampling */
15 #define PERF_EVENT_CPUM_SF_DIAG 0xBD000 /* Event: Combined-sampling */
27 return 0; in cpumsf_info_priv_size()
37 return 0; in cpumsf_info_fill()
43 return 0; in cpumsf_reference()
72 return 0; in cpumsf_recording_options()
80 return 0; in cpumsf_parse_snapshot_options()
92 int diagnose = 0; in auxtrace_record__init()
94 *err = 0; in auxtrace_record__init()
95 if (evlist->core.nr_entries == 0) in auxtrace_record__init()
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dgardena_smart_gateway_mt7688.dts18 memory@0 {
20 reg = <0x0 0x8000000>;
27 pinctrl-0 = <&pinmux_gpio_gpio>; /* GPIO11 */
40 pinctrl-0 = <&pinmux_pwm0_gpio>, /* GPIO18 */
130 pinctrl-0 = <&pinmux_spi_spi>, <&pinmux_spi_cs1_cs>;
132 flash@0 {
134 reg = <0>;
142 partition@0 {
144 reg = <0x0 0xa0000>;
150 reg = <0xa0000 0x10000>;
[all …]
/openbmc/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629-rfb.dts41 reg = <0x40000000 0x10000000>;
65 pinctrl-0 = <&eth_pins>;
69 gmac0: mac@0 {
71 reg = <0>;
89 #size-cells = <0>;
91 phy0: ethernet-phy@0 {
92 reg = <0>;
99 pinctrl-0 = <&i2c_pins>;
105 pinctrl-0 = <&qspi_pins>;
108 flash@0 {
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dimx-regs.h11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmicro-support-card.c14 #define MICRO_SUPPORT_CARD_BASE 0x43f00000
15 #define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
16 #define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
17 #define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
18 #define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
19 #define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
22 * 0: reset deassert, 1: reset
24 * bit[0]: LAN, I2C, LED
29 writel(0x00010000, MICRO_SUPPORT_CARD_RESET); in support_card_reset_deassert()
34 writel(0x00020003, MICRO_SUPPORT_CARD_RESET); in support_card_reset()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra186-mc.yaml27 pattern: "^memory-controller@[0-9a-f]+$"
62 "^external-memory-controller@[0-9a-f]+$":
95 const: 0
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_mixer.h18 #define SUN8I_MIXER_GLOBAL_CTL 0x0
19 #define SUN8I_MIXER_GLOBAL_STATUS 0x4
20 #define SUN8I_MIXER_GLOBAL_DBUFF 0x8
21 #define SUN8I_MIXER_GLOBAL_SIZE 0xc
23 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
25 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
27 #define DE2_MIXER_UNIT_SIZE 0x6000
28 #define DE3_MIXER_UNIT_SIZE 0x3000
30 #define DE2_BLD_BASE 0x1000
31 #define DE2_CH_BASE 0x2000
[all …]

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