Lines Matching +full:0 +full:xb0000
94 u8 res[0xc];
112 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
113 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
115 #define SUNXI_DE2_MUX_GLB_REGS 0x00000
116 #define SUNXI_DE2_MUX_BLD_REGS 0x01000
117 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000
118 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000
119 #define SUNXI_DE2_MUX_VSU_REGS 0x20000
120 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000
121 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000
122 #define SUNXI_DE2_MUX_GSU3_REGS 0x50000
123 #define SUNXI_DE2_MUX_FCE_REGS 0xa0000
124 #define SUNXI_DE2_MUX_BWS_REGS 0xa2000
125 #define SUNXI_DE2_MUX_LTI_REGS 0xa4000
126 #define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
127 #define SUNXI_DE2_MUX_ASE_REGS 0xa8000
128 #define SUNXI_DE2_MUX_FCC_REGS 0xaa000
129 #define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
134 #define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0)
135 #define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
136 #define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)