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/openbmc/linux/Documentation/i2c/busses/
H A Dscx200_acb.rst15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfpga_manager_gen5.h10 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
11 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
18 #define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
24 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
27 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
28 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
29 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
30 #define FPGAMGRREGS_MODE_INITPHASE 0x3
31 #define FPGAMGRREGS_MODE_USERMODE 0x4
32 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h9 #define MMDC0 0
12 #define MMDC_MDCTL 0x0
13 #define MMDC_MDPDC 0x4
14 #define MMDC_MDOTC 0x8
15 #define MMDC_MDCFG0 0xC
16 #define MMDC_MDCFG1 0x10
17 #define MMDC_MDCFG2 0x14
18 #define MMDC_MDMISC 0x18
19 #define MMDC_MDSCR 0x1C
20 #define MMDC_MDREF 0x20
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.h32 CX18_AV_SVIDEO_LUMA1 = 0x10,
33 CX18_AV_SVIDEO_LUMA2 = 0x20,
34 CX18_AV_SVIDEO_LUMA3 = 0x30,
35 CX18_AV_SVIDEO_LUMA4 = 0x40,
36 CX18_AV_SVIDEO_LUMA5 = 0x50,
37 CX18_AV_SVIDEO_LUMA6 = 0x60,
38 CX18_AV_SVIDEO_LUMA7 = 0x70,
39 CX18_AV_SVIDEO_LUMA8 = 0x80,
40 CX18_AV_SVIDEO_CHROMA4 = 0x400,
41 CX18_AV_SVIDEO_CHROMA5 = 0x500,
[all …]
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_com_phycfg.h10 #define PathA 0x0 /* Useless */
11 #define PathB 0x1
12 #define PathC 0x2
13 #define PathD 0x3
16 CCK = 0,
21 #define MAX_POWER_INDEX 0x3F
24 TXPWR_LMT_FCC = 0,
34 /* 0x870~0x877[8 bytes] */
37 /* 0x860~0x86f [16 bytes] */
40 /* 0x860~0x86f [16 bytes] */
[all …]
/openbmc/u-boot/board/wandboard/
H A Dspl.c27 * 0x30 == 40 Ohm
28 * 0x28 == 48 Ohm
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
33 #define IMX6QP_DRIVE_STRENGTH 0x28
44 .dram_sdba2 = 0x00000000,
74 .dram_sdba2 = 0x00000000,
97 .grp_ddr_type = 0x000c0000,
98 .grp_ddrmode_ctl = 0x00020000,
99 .grp_ddrpke = 0x00000000,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-icev2.dts29 reg = <0x80000000 0x10000000>; /* 256 MB */
32 vbat: fixedregulator@0 {
51 leds@0 {
54 led@0 {
56 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
107 pinctrl-0 = <&user_leds>;
109 led@0 {
152 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
153 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
154 AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
47 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
48 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
54 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
55 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
56 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
57 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/openbmc/linux/arch/sh/boards/
H A Dboard-sh7757lcr.c27 .start = 0xffec005c, /* PUDR */
28 .end = 0xffec005c,
32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
51 #define GBECONT 0xffc10100
56 if (((unsigned long)addr & 0x00000fff) < 0x0800) in sh7757_eth_set_mdio_gate()
64 .start = 0xfef00000,
65 .end = 0xfef001ff,
68 .start = evt2irq(0xc80),
69 .end = evt2irq(0xc80),
82 .id = 0,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c19 UNUSED = 0,
33 INTC_VECT(DMAC1, 0x800), INTC_VECT(DMAC1, 0x820),
34 INTC_VECT(DMAC1, 0x840), INTC_VECT(DMAC1, 0x860),
35 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
36 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
37 INTC_VECT(SCIF1, 0x900), INTC_VECT(SCIF1, 0x920),
38 INTC_VECT(SCIF1, 0x940), INTC_VECT(SCIF1, 0x960),
39 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
41 INTC_VECT(IPSEC, 0xbe0),
43 INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
[all …]
H A Dsetup-sh7705.c20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
H A Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
/openbmc/linux/include/media/drv-intf/
H A Dcx25840.h45 CX25840_SVIDEO_LUMA1 = 0x10,
46 CX25840_SVIDEO_LUMA2 = 0x20,
47 CX25840_SVIDEO_LUMA3 = 0x30,
48 CX25840_SVIDEO_LUMA4 = 0x40,
49 CX25840_SVIDEO_LUMA5 = 0x50,
50 CX25840_SVIDEO_LUMA6 = 0x60,
51 CX25840_SVIDEO_LUMA7 = 0x70,
52 CX25840_SVIDEO_LUMA8 = 0x80,
53 CX25840_SVIDEO_CHROMA4 = 0x400,
54 CX25840_SVIDEO_CHROMA5 = 0x500,
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dsrc.c19 #define SRC_SCR 0x000
20 #define SRC_GPR1_V1 0x020
21 #define SRC_GPR1_V2 0x074
23 #define BP_SRC_SCR_WARM_RESET_ENABLE 0
32 #define SRC_A7RCR1 0x008
34 #define GPC_CPU_PGC_SW_PUP_REQ 0xf0
35 #define GPC_CPU_PGC_SW_PDN_REQ 0xfc
36 #define GPC_PGC_C1 0x840
37 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
78 return 0; in imx_src_reset_module()
[all …]
/openbmc/qemu/hw/intc/
H A Dpnv_xive_regs.h13 /* IC register offsets 0x0 - 0x400 */
14 #define CQ_SWI_CMD_HIST 0x020
15 #define CQ_SWI_CMD_POLL 0x028
16 #define CQ_SWI_CMD_BCAST 0x030
17 #define CQ_SWI_CMD_ASSIGN 0x038
18 #define CQ_SWI_CMD_BLK_UPD 0x040
19 #define CQ_SWI_RSP 0x048
20 #define CQ_CFG_PB_GEN 0x050
22 #define CQ_MSGSND 0x058
23 #define CQ_CNPM_SEL 0x078
[all …]
/openbmc/linux/drivers/net/dsa/
H A Drzn1_a5psw.h18 #define A5PSW_REVISION 0x0
19 #define A5PSW_PORT_OFFSET(port) (0x400 * (port))
21 #define A5PSW_PORT_ENA 0x8
26 #define A5PSW_UCAST_DEF_MASK 0xC
28 #define A5PSW_VLAN_VERIFY 0x10
29 #define A5PSW_VLAN_VERI_SHIFT 0
32 #define A5PSW_BCAST_DEF_MASK 0x14
33 #define A5PSW_MCAST_DEF_MASK 0x18
35 #define A5PSW_INPUT_LEARN 0x1C
39 #define A5PSW_MGMT_CFG 0x20
[all …]
/openbmc/linux/include/video/
H A Dsh_mobile_lcdc.h8 #define _LDDCKR 0x410
9 #define LDDCKR_ICKSEL_BUS (0 << 16)
15 #define _LDDCKSTPR 0x414
16 #define _LDINTR 0x468
22 #define LDINTR_VES (1 << 0)
23 #define LDINTR_STATUS_MASK (0xff << 0)
24 #define _LDSR 0x46c
28 #define _LDCNT1R 0x470
29 #define LDCNT1R_DE (1 << 0)
30 #define _LDCNT2R 0x474
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
173 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
198 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
202 regf.lsb = 0; in _rsnd_gen_regmap_init()
215 return 0; in _rsnd_gen_regmap_init()
224 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850), in rsnd_gen4_probe()
225 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858), in rsnd_gen4_probe()
226 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890), in rsnd_gen4_probe()
[all …]

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