/openbmc/linux/Documentation/devicetree/bindings/pci/ |
H A D | mvebu-pci.txt | 23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s 32 registers area. This range entry translates the '0x82000000 0 r' PCI 33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part 34 of the internal register window (as identified by MBUS_ID(0xf0, 35 0x01)). 39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0 79 value is 0. 99 bus-range = <0x00 0xff>; 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ [all …]
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H A D | nvidia,tegra20-pcie.txt | 27 - cell 0 specifies the bus and device numbers of the root port: 30 - cell 1 denotes the upper 32 address bits and should be 0 45 - 0x81000000: I/O memory region 46 - 0x82000000: non-prefetchable memory region 47 - 0xc2000000: prefetchable memory region 73 - pinctrl-0: phandle for the default/active state of pin configurations. 104 - If lanes 0 to 3 are used: 150 - Root port 0 uses 4 lanes, root port 1 is unused. 158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes. 171 reg = <0x80003000 0x00000800 /* PADS registers */ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | armada-xp-mv78460.dtsi | 65 #size-cells = <0>; 68 cpu@0 { 71 reg = <0>; 72 clocks = <&cpuclk 0>; 103 * MV78460 has 4 PCIe units Gen2.0: Two units can be 116 bus-range = <0x00 0xff>; 119 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 120 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 121 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 122 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-xp-mv78260.dtsi | 64 #size-cells = <0>; 67 cpu@0 { 70 reg = <0>; 71 clocks = <&cpuclk 0>; 86 * MV78260 has 3 PCIe units Gen2.0: Two units can be 99 bus-range = <0x00 0xff>; 102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-385.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 45 bus-range = <0x00 0xff>; 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | armada-xp-mv78230.dtsi | 63 #size-cells = <0>; 66 cpu@0 { 69 reg = <0>; 70 clocks = <&cpuclk 0>; 85 * MV78230 has 2 PCIe units Gen2.0: One unit can be 98 bus-range = <0x00 0xff>; 101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ [all …]
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H A D | kirkwood-98dx4122.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6281.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6192.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-xp-mv78460.dtsi | 28 #size-cells = <0>; 31 cpu@0 { 34 reg = <0>; 35 clocks = <&cpuclk 0>; 66 * MV78460 has 4 PCIe units Gen2.0: Two units can be 79 bus-range = <0x00 0xff>; 82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-xp-mv78260.dtsi | 27 #size-cells = <0>; 30 cpu@0 { 33 reg = <0>; 34 clocks = <&cpuclk 0>; 49 * MV78260 has 3 PCIe units Gen2.0: Two units can be 62 bus-range = <0x00 0xff>; 65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ [all …]
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H A D | armada-385.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 45 bus-range = <0x00 0xff>; 48 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 49 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 50 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 51 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | armada-xp-mv78230.dtsi | 26 #size-cells = <0>; 29 cpu@0 { 32 reg = <0>; 33 clocks = <&cpuclk 0>; 48 * MV78230 has 2 PCIe units Gen2.0: One unit can be 61 bus-range = <0x00 0xff>; 64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ [all …]
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H A D | armada-380.dtsi | 20 #size-cells = <0>; 23 cpu@0 { 26 reg = <0>; 46 bus-range = <0x00 0xff>; 49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ [all …]
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H A D | kirkwood-6282.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ 21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; 23 pcie0: pcie@1,0 { 25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; [all …]
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H A D | armada-39x.dtsi | 32 #size-cells = <0>; 35 cpu@0 { 38 reg = <0>; 59 pcie-mem-aperture = <0xe0000000 0x8000000>; 60 pcie-io-aperture = <0xe8000000 0x100000>; 64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 75 reg = <0x8000 0x1000>; 78 arm,double-linefill-incr = <0>; 79 arm,double-linefill-wrap = <0>; [all …]
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H A D | kirkwood-98dx4122.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6281.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | kirkwood-6192.dtsi | 12 bus-range = <0x00 0xff>; 15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; 19 pcie0: pcie@1,0 { 21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; 22 reg = <0x0800 0 0 0 0>; 26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 27 0x81000000 0 0 0x81000000 0x1 0 1 0>; 28 bus-range = <0x00 0xff>; [all …]
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H A D | armada-370.dtsi | 35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>; 47 bus-range = <0x00 0xff>; 50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 57 pcie0: pcie@1,0 { 59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; [all …]
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/openbmc/u-boot/board/ti/am335x/ |
H A D | README | 68 U-Boot # load mmc 0 0x82000000 MLO 69 U-Boot # nand write 0x82000000 0x00000 0x20000 70 U-Boot # nand write 0x82000000 0x20000 0x20000 71 U-Boot # nand write 0x82000000 0x40000 0x20000 72 U-Boot # nand write 0x82000000 0x60000 0x20000 74 U-Boot # load mmc 0 0x82000000 u-boot.img 75 U-Boot # nand write 0x82000000 0x80000 0x60000 77 U-Boot # load mmc 0 0x82000000 uImage 78 U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} 80 U-Boot # load mmc 0 0x82000000 filesystem.img [all …]
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/openbmc/u-boot/doc/ |
H A D | README.commands.spl | 20 nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ 22 nand erase 0x680000 0x20000 /* erase - one page */ 23 nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ 27 nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ 28 tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ 29 spl export fdt 0x82000000 - 0x80000100 /* export FDT */ 30 nand erase 0x680000 0x20000 /* erase - one page */ 31 nand write <adress shown by spl export> 0x680000 0x20000
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/openbmc/u-boot/include/configs/ |
H A D | sniper.h | 46 #define CONFIG_SYS_SDRAM_BASE 0x80000000 67 #define CONFIG_SPL_TEXT_BASE 0x40200000 70 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 72 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 105 "kernel_addr_r=0x82000000\0" \ 106 "loadaddr=0x82000000\0" \ 107 "fdt_addr_r=0x88000000\0" \ 108 "fdtaddr=0x88000000\0" \ 109 "ramdisk_addr_r=0x88080000\0" \ 110 "pxefile_addr_r=0x80100000\0" \ [all …]
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H A D | kc1.h | 23 #define CONFIG_SYS_PL310_BASE 0x48242000 44 #define CONFIG_SYS_SDRAM_BASE 0x80000000 73 #define CONFIG_SPL_TEXT_BASE 0x40300000 76 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 78 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 112 "kernel_addr_r=0x82000000\0" \ 113 "loadaddr=0x82000000\0" \ 114 "fdt_addr_r=0x88000000\0" \ 115 "fdtaddr=0x88000000\0" \ 116 "ramdisk_addr_r=0x88080000\0" \ [all …]
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