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/openbmc/linux/drivers/media/usb/gspca/
H A Dspca508.c23 #define CreativeVista 0
51 .priv = 0},
62 {0x0000, 0x870b},
64 {0x0020, 0x8112}, /* Video drop enable, ISO streaming disable */
65 {0x0003, 0x8111}, /* Reset compression & memory */
66 {0x0000, 0x8110}, /* Disable all outputs */
67 /* READ {0x0000, 0x8114} -> 0000: 00 */
68 {0x0000, 0x8114}, /* SW GPIO data */
69 {0x0008, 0x8110}, /* Enable charge pump output */
70 {0x0002, 0x8116}, /* 200 kHz pump clock */
[all …]
H A Dspca561.c37 #define Rev012A 0
64 .priv = 0},
87 .priv = 0},
112 #define SPCA561_INDEX_I2C_BASE 0x8800
113 #define SPCA561_SNAPBIT 0x20
114 #define SPCA561_SNAPCTRL 0x40
117 {0x0000, 0x8114}, /* Software GPIO output data */
118 {0x0001, 0x8114}, /* Software GPIO output data */
119 {0x0000, 0x8112}, /* Some kind of reset */
123 {0x0003, 0x8701}, /* PCLK clock delay adjustment */
[all …]
/openbmc/u-boot/board/sysam/amcore/
H A Damcore.c23 out_be16(&sim->par, 0x300); in init_lcd()
27 out_be16(&gpio->paddr, 0xfcff); in init_lcd()
28 out_be16(&gpio->padat, 0x0c00); in init_lcd()
38 return 0; in checkboard()
61 * Memory block 0: 16 MB of SDRAM at address $00000000 in dram_init()
64 * Memory block 0 wired as follows: in dram_init()
81 /* 0x8000 is the faster option */ in dram_init()
82 out_be16(&dc->dcr, 0x8200 | RC); in dram_init()
85 * DACR0, page mode continuous, CMD on A20 0x0300 in dram_init()
87 out_be32(&dc->dacr0, 0x00003304); in dram_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,qcm2290.yaml90 reg = <0x01880000 0x60200>;
123 reg = <0x01900000 0x8200>;
132 reg = <0x04480000 0x80000>;
/openbmc/linux/tools/perf/tests/attr/
H A Dtest-stat-default33 type=0
34 config=0
40 type=0
46 type=0
53 type=0
60 type=0
67 type=0
71 # PERF_TYPE_RAW / slots (0x400)
80 # PERF_TYPE_RAW / topdown-retiring (0x8000)
86 disabled=0
[all …]
H A Dtest-stat-detailed-134 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
H A Dtest-stat-detailed-234 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
H A Dtest-stat-detailed-334 type=0
35 config=0
41 type=0
48 type=0
55 type=0
62 type=0
69 type=0
73 # PERF_TYPE_RAW / slots (0x400)
82 # PERF_TYPE_RAW / topdown-retiring (0x8000)
88 disabled=0
[all …]
/openbmc/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h39 #define PATREGSIZE 384 /* Pattern register size. 384 bytes @ 0x8300 */
40 #define BR(x) (0x8200 | (x) << 2)
41 #define PBR(x) (0x8300 | (x) << 2)
44 #define BITBLT 0x00000000 /* Blit */
45 #define COLOREXP 0x00000001 /* Color expand */
46 #define ENCOLOREXP 0x00000002 /* Enhanced color expand */
47 #define MULTIPLE_SCANLINE 0x00000003 /* ? */
48 #define LINE 0x00000004 /* Draw line */
49 #define TRAPAZOID_FILL 0x00000005 /* Fill trapezoid */
50 #define TRANSPARENT_BITBLT 0x00000006 /* Transparent Blit */
[all …]
/openbmc/u-boot/board/terasic/de0-nano-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
18 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
35 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
44 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
45 #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
[all …]
/openbmc/u-boot/board/ebv/socrates/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/devboards/dbm-soc1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/samtec/vining_fpga/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/sr1500/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/de1-soc/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/terasic/sockit/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/is1/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/cyclone5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/u-boot/board/terasic/de10-nano/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
[all …]
/openbmc/u-boot/board/altera/arria5-socdk/qts/
H A Dsdram_config.h10 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmvme5100.dts26 #size-cells = <0>;
30 reg = <0x0>;
44 reg = <0x0 0x20000000>;
51 ranges = <0x0 0xfef80000 0x10000>;
52 reg = <0xfef80000 0x10000>;
57 reg = <0x8000 0x80>;
68 reg = <0x8200 0x80>;
78 #address-cells = <0>;
82 reg = <0xf3f80000 0x40000>;
92 reg = <0xfec00000 0x400000>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/drivers/net/usb/
H A Dsr9800.h16 #define SR_CMD_SET_SW_MII 0x06
18 #define SR_CMD_READ_MII_REG 0x07
20 #define SR_CMD_WRITE_MII_REG 0x08
22 #define SR_CMD_SET_HW_MII 0x0a
24 #define SR_CMD_READ_EEPROM 0x0b
26 #define SR_CMD_WRITE_EEPROM 0x0c
28 #define SR_CMD_WRITE_ENABLE 0x0d
30 #define SR_CMD_WRITE_DISABLE 0x0e
32 #define SR_CMD_READ_RX_CTL 0x0f
33 #define SR_RX_CTL_PRO (1 << 0)
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
/openbmc/linux/drivers/media/usb/au0828/
H A Dau0828-cards.c20 au0828_set(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
22 au0828_clear(dev, REG_000, 0x10); in hvr950q_cs5340_audio()
39 .tuner_addr = 0x61,
66 .tuner_addr = 0x61,
93 .tuner_addr = 0x61,
99 .tuner_addr = 0x61,
105 .tuner_addr = 0x60,
124 if (command == 0) { in au0828_tuner_callback()
131 return 0; in au0828_tuner_callback()
139 return 0; /* Should never be here */ in au0828_tuner_callback()
[all …]

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