Lines Matching +full:0 +full:x8200
13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
28 #define HYDRA_RESET_XBAR_REG 0x80030020
29 #define HYDRA_RESET_XBAR_DATA 0x00000000
31 #define HYDRA_MODULES_CLK_1_REG 0x80030014
32 #define HYDRA_DISABLE_CLK_1 0x00000000
34 #define HYDRA_MODULES_CLK_2_REG 0x8003001C
35 #define HYDRA_DISABLE_CLK_2 0x0000000B
37 #define HYDRA_PRCM_ROOT_CLK_REG 0x80030018
38 #define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000
40 #define HYDRA_CPU_RESET_CHECK_REG 0x80030008
41 #define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 /* <bit 30> */
43 #define HYDRA_SKU_ID_REG 0x90000190
45 #define FW_DL_SIGN_ADDR 0x3FFFEAE0
48 #define HYDRA_HEAR_BEAT 0x3FFFEDDC
51 #define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8
52 #define HYDRA_FW_RC_VERSION 0x3FFFCFAC
55 #define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2
58 #define HYDRA_TEMPARATURE 0x3FFFEDB4
61 /* Demod 0 status base address */
62 #define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C
64 /* Tuner 0 status base address */
65 #define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C
67 #define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C
70 #define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100)
71 #define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40)
74 #define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C
75 #define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650
76 #define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654
78 #define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658
79 #define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C
80 #define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660
81 #define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664
82 #define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668
83 #define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C
85 #define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670
86 #define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674
87 #define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678
88 #define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C
89 #define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680
90 #define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684
91 #define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688
93 #define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C
94 #define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E
96 #define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690
97 #define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694
98 #define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698
100 #define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C
101 #define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0
102 #define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4
103 #define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8
105 /* Debug-purpose DVB-S DMD 0 */
106 #define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 /* corrected RS Errors: 1st i…
107 #define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC /* uncorrected RS Errors: 1st…
108 #define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0
109 #define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4
111 #define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC
112 #define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0
113 #define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4
114 #define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8
115 #define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704
116 #define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708
119 #define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 /* DMD 0: 1st iteration BER co…
120 #define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 /* DMD 0: 2nd iteration BER co…
122 #define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C
123 #define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740
124 #define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744
126 #define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748
129 #define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C
130 #define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50
131 #define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54
132 #define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58
133 #define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C
134 #define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78
139 #define HYDRA_VERSION 0x3FFFEDB8
140 #define HYDRA_DEMOD0_VERSION 0x3FFFEDBC
141 #define HYDRA_DEMOD1_VERSION 0x3FFFEDC0
142 #define HYDRA_DEMOD2_VERSION 0x3FFFEDC4
143 #define HYDRA_DEMOD3_VERSION 0x3FFFEDC8
144 #define HYDRA_DEMOD4_VERSION 0x3FFFEDCC
145 #define HYDRA_DEMOD5_VERSION 0x3FFFEDD0
146 #define HYDRA_DEMOD6_VERSION 0x3FFFEDD4
147 #define HYDRA_DEMOD7_VERSION 0x3FFFEDD8
148 #define HYDRA_HEAR_BEAT 0x3FFFEDDC
149 #define HYDRA_SKU_MGMT 0x3FFFEBC0
151 #define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000
152 #define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000
155 #define HYDRA_TS_CTRL_BASE_ADDR 0x90700000
157 #define MPEG_MUX_MODE_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
159 #define MPEG_MUX_MODE_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)
161 #define PID_BANK_SEL_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
162 #define PID_BANK_SEL_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
164 #define MPEG_CLK_GATED_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x20)
166 #define MPEG_CLK_ALWAYS_ON_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)
168 #define HYDRA_REGULAR_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
170 #define HYDRA_FIXED_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)
172 #define HYDRA_REGULAR_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
174 #define HYDRA_FIXED_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)
176 #define FIXED_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)
177 #define FIXED_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)
178 #define FIXED_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)
179 #define FIXED_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)
181 #define FIXED_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)
182 #define FIXED_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)
183 #define FIXED_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)
184 #define FIXED_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)
186 #define REGULAR_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)
187 #define REGULAR_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)
188 #define REGULAR_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)
189 #define REGULAR_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)
191 #define REGULAR_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)
192 #define REGULAR_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)
193 #define REGULAR_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)
194 #define REGULAR_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)
198 #define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188
201 #define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C
203 #define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044
204 #define XPT_NCO_COUNT_BASEADDR 0x90700238
206 #define XPT_NCO_COUNT_BASEADDR1 0x9070023C
210 #define XPT_PID_BASEADDR 0x90708000
212 #define XPT_PID_REMAP_BASEADDR 0x90708004
214 #define XPT_KNOWN_PID_BASEADDR 0x90709000
216 #define XPT_PID_BASEADDR1 0x9070A000
218 #define XPT_PID_REMAP_BASEADDR1 0x9070A004
220 #define XPT_KNOWN_PID_BASEADDR1 0x9070B000
222 #define XPT_BERT_LOCK_BASEADDR 0x907000B8
224 #define XPT_BERT_BASEADDR 0x907000BC
226 #define XPT_BERT_INVERT_BASEADDR 0x907000C0
228 #define XPT_BERT_HEADER_BASEADDR 0x907000C4
230 #define XPT_BERT_BASEADDR1 0x907000C8
232 #define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC
234 #define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0
236 #define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4
238 #define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8
240 #define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC
242 #define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0
244 #define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4
246 #define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8
248 #define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC
250 #define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0
252 #define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4
254 #define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8
256 #define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC
258 #define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100
260 #define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104
262 #define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108
264 #define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C
266 #define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110
268 #define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114
270 #define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118
272 #define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C
274 #define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120
276 #define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124
278 #define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128
280 #define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C
282 #define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130
284 #define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134
286 #define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138
288 #define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C
290 #define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140
292 #define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144
294 #define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148
296 #define XPT_BERT_ERROR_BASEADDR 0x9070014C
298 #define XPT_BERT_ANALYZER_BASEADDR 0x90700150
300 #define XPT_BERT_ANALYZER_BASEADDR1 0x90700154
302 #define XPT_BERT_ANALYZER_BASEADDR2 0x90700158
304 #define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C
306 #define XPT_BERT_ANALYZER_BASEADDR4 0x90700160
308 #define XPT_BERT_ANALYZER_BASEADDR5 0x90700164
310 #define XPT_BERT_ANALYZER_BASEADDR6 0x90700168
312 #define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C
314 #define XPT_BERT_ANALYZER_BASEADDR8 0x90700170
316 #define XPT_BERT_ANALYZER_BASEADDR9 0x90700174
318 #define XPT_DMD0_BASEADDR 0x9070024C
321 #define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) /* 1: DISABLE, 0:ENAB…
322 #define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4
324 #define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4
326 #define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4
328 #define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4
330 #define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104
332 #define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0
334 #define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4
336 #define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4
338 #define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4
340 #define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498
342 #define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498
344 #define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498
346 #define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498
348 #define WDT_WD_INT_BASEADDR 0x8002000C
350 #define FSK_TX_FTM_BASEADDR 0x80090000
352 #define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018
354 #define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040
356 #define DMD_TEI_BASEADDR 0x3FFFEBE0