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Searched +full:0 +full:x81800000 (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,k3-dsp-rproc.yaml148 mailbox0_cluster3: mailbox-0 {
160 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
161 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
162 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
163 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
168 reg = <0x4d 0x80800000 0x00 0x00048000>,
169 <0x4d 0x80e00000 0x00 0x00008000>,
170 <0x4d 0x80f00000 0x00 0x00008000>;
174 ti,sci-proc-ids = <0x03 0xFF>;
185 reg = <0x00 0x64800000 0x00 0x00080000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/openbmc/u-boot/doc/
H A DREADME.ubispl60 #define SPL_FINFO_ADDR 0x80800000
61 #define SPL_DTB_LOAD_ADDR 0x81800000
62 #define SPL_KERNEL_LOAD_ADDR 0x82000000
68 .vol_id = 0, /* kernel volume */
91 * part_spl { .start = 0, .end = 4 }
/openbmc/qemu/hw/microblaze/
H A Dpetalogix_s3adsp1800_mmu.c46 #define MEMORY_BASEADDR 0x90000000
47 #define FLASH_BASEADDR 0xa0000000
48 #define GPIO_BASEADDR 0x81400000
49 #define INTC_BASEADDR 0x81800000
50 #define TIMER_BASEADDR 0x83c00000
51 #define UARTLITE_BASEADDR 0x84000000
52 #define ETHLITE_BASEADDR 0x81000000
54 #define TIMER_IRQ 0
85 memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); in petalogix_s3adsp1800_init()
91 dinfo = drive_get(IF_PFLASH, 0, 0); in petalogix_s3adsp1800_init()
[all …]
H A Dpetalogix_ml605_mmu.c53 #define SPI_BASEADDR 0x40a00000
54 #define MEMORY_BASEADDR 0x50000000
55 #define FLASH_BASEADDR 0x86000000
56 #define INTC_BASEADDR 0x81800000
57 #define TIMER_BASEADDR 0x83c00000
58 #define UART16550_BASEADDR 0x83e00000
59 #define AXIENET_BASEADDR 0x82780000
60 #define AXIDMA_BASEADDR 0x84600000
62 #define AXIDMA_IRQ1 0
99 memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); in petalogix_ml605_init()
[all …]
/openbmc/qemu/hw/ppc/
H A Dvirtex_ml507.c50 #define EPAPR_MAGIC (0x45504150)
53 #define INTC_BASEADDR 0x81800000
54 #define UART16550_BASEADDR 0x83e01003
55 #define TIMER_BASEADDR 0x83c00000
56 #define PFLASH_BASEADDR 0xfc000000
80 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); in ppc440_init_xilinx()
107 * r4: 0 in main_cpu_reset()
108 * r5: 0 in main_cpu_reset()
111 * r8: 0 in main_cpu_reset()
112 * r9: 0 in main_cpu_reset()
[all …]
/openbmc/qemu/pc-bios/
H A Dpetalogix-s3adsp1800.dts11 #address-cells = <0x01>;
12 #size-cells = <0x01>;
18 reg = <0x90000000 0x8000000>;
27 #address-cells = <0x01>;
28 #size-cells = <0x00>;
29 #cpus = <0x01>;
31 cpu@0 {
32 clock-frequency = <0x3b9aca0>;
34 d-cache-baseaddr = <0x90000000>;
35 d-cache-highaddr = <0x97ffffff>;
[all …]
H A Dpetalogix-ml605.dts11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
18 reg = < 0x50000000 0x10000000 >;
32 #address-cells = < 0x01 >;
33 #cpus = < 0x01 >;
34 #size-cells = < 0x00 >;
36 cpu@0 {
37 clock-frequency = < 0xbebc200 >;
39 d-cache-baseaddr = < 0x50000000 >;
40 d-cache-highaddr = < 0x5fffffff >;
[all …]
/openbmc/linux/arch/microblaze/boot/dts/
H A Dsystem.dts24 reg = < 0x90000000 0x10000000 >;
32 stdout-path = "/plb@0/serial@84000000";
36 #cpus = <0x1>;
37 #size-cells = <0>;
38 microblaze_0: cpu@0 {
41 d-cache-baseaddr = <0x90000000>;
42 d-cache-highaddr = <0x9fffffff>;
43 d-cache-line-size = <0x10>;
44 d-cache-size = <0x2000>;
46 i-cache-baseaddr = <0x90000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8953.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
[all …]