Lines Matching +full:0 +full:x81800000

50 #define EPAPR_MAGIC    (0x45504150)
53 #define INTC_BASEADDR 0x81800000
54 #define UART16550_BASEADDR 0x83e01003
55 #define TIMER_BASEADDR 0x83c00000
56 #define PFLASH_BASEADDR 0xfc000000
80 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); in ppc440_init_xilinx()
107 * r4: 0 in main_cpu_reset()
108 * r5: 0 in main_cpu_reset()
111 * r8: 0 in main_cpu_reset()
112 * r9: 0 in main_cpu_reset()
120 booke_set_tlb(&env->tlb.tlbe[0], 0, 0, 1U << 31); in main_cpu_reset()
121 booke_set_tlb(&env->tlb.tlbe[1], 0x80000000, 0x80000000, 1U << 31); in main_cpu_reset()
157 return 0; in xilinx_load_device_tree()
162 if (r < 0) { in xilinx_load_device_tree()
168 if (r < 0) { in xilinx_load_device_tree()
174 if (r < 0) in xilinx_load_device_tree()
187 hwaddr initrd_base = 0; in virtex_init()
188 int initrd_size = 0; in virtex_init()
193 hwaddr ram_base = 0; in virtex_init()
213 dinfo = drive_get(IF_PFLASH, 0, 0); in virtex_init()
216 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); in virtex_init()
220 qdev_prop_set_uint32(dev, "kind-of-intr", 0); in virtex_init()
222 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); in virtex_init()
223 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); in virtex_init()
224 for (i = 0; i < 32; i++) { in virtex_init()
229 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); in virtex_init()
233 qdev_prop_set_uint32(dev, "one-timer-only", 0); in virtex_init()
236 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); in virtex_init()
237 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); in virtex_init()
246 0, 0); in virtex_init()
247 boot_info.bootstrap_pc = entry & 0x00ffffff; in virtex_init()
249 if (kernel_size < 0) { in virtex_init()
250 boot_offset = 0x1200000; in virtex_init()
267 if (initrd_size < 0) { in virtex_init()